Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176760 |
1 |
|
|
T2 |
2507 |
|
T8 |
2903 |
|
T21 |
113 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
88857 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
66750 |
1 |
|
|
T2 |
58 |
|
T8 |
92 |
|
T21 |
111 |
seven_bytes |
3029 |
1 |
|
|
T2 |
61 |
|
T8 |
74 |
|
T18 |
43 |
six_bytes |
3029 |
1 |
|
|
T2 |
68 |
|
T8 |
86 |
|
T18 |
36 |
five_bytes |
3052 |
1 |
|
|
T2 |
70 |
|
T8 |
91 |
|
T18 |
40 |
four_bytes |
3048 |
1 |
|
|
T2 |
71 |
|
T8 |
69 |
|
T18 |
42 |
three_bytes |
2981 |
1 |
|
|
T2 |
59 |
|
T8 |
81 |
|
T18 |
46 |
two_bytes |
3035 |
1 |
|
|
T2 |
58 |
|
T8 |
81 |
|
T18 |
37 |
one_byte |
2979 |
1 |
|
|
T2 |
61 |
|
T8 |
79 |
|
T18 |
35 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173384 |
1 |
|
|
T2 |
2481 |
|
T8 |
2871 |
|
T21 |
109 |
auto[1] |
3376 |
1 |
|
|
T2 |
26 |
|
T8 |
32 |
|
T21 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176760 |
1 |
|
|
T2 |
2507 |
|
T8 |
2903 |
|
T21 |
113 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176747 |
1 |
|
|
T2 |
2507 |
|
T8 |
2903 |
|
T21 |
113 |
auto[1] |
13 |
1 |
|
|
T157 |
1 |
|
T158 |
1 |
|
T159 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1202 |
1 |
|
|
T2 |
8 |
|
T8 |
8 |
|
T21 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3376 |
1 |
|
|
T2 |
26 |
|
T8 |
32 |
|
T21 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174056 |
1 |
|
|
T2 |
3751 |
|
T7 |
643 |
|
T8 |
902 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90511 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62053 |
1 |
|
|
T2 |
107 |
|
T7 |
21 |
|
T8 |
33 |
seven_bytes |
3129 |
1 |
|
|
T2 |
107 |
|
T7 |
21 |
|
T8 |
30 |
six_bytes |
3082 |
1 |
|
|
T2 |
79 |
|
T7 |
18 |
|
T8 |
20 |
five_bytes |
3144 |
1 |
|
|
T2 |
97 |
|
T7 |
17 |
|
T8 |
21 |
four_bytes |
3074 |
1 |
|
|
T2 |
106 |
|
T7 |
18 |
|
T8 |
29 |
three_bytes |
3019 |
1 |
|
|
T2 |
104 |
|
T7 |
12 |
|
T8 |
29 |
two_bytes |
2998 |
1 |
|
|
T2 |
87 |
|
T7 |
13 |
|
T8 |
15 |
one_byte |
3046 |
1 |
|
|
T2 |
90 |
|
T7 |
16 |
|
T8 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170696 |
1 |
|
|
T2 |
3705 |
|
T7 |
637 |
|
T8 |
886 |
auto[1] |
3360 |
1 |
|
|
T2 |
46 |
|
T7 |
6 |
|
T8 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174056 |
1 |
|
|
T2 |
3751 |
|
T7 |
643 |
|
T8 |
902 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174044 |
1 |
|
|
T2 |
3751 |
|
T7 |
643 |
|
T8 |
902 |
auto[1] |
12 |
1 |
|
|
T160 |
1 |
|
T161 |
1 |
|
T162 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1174 |
1 |
|
|
T2 |
9 |
|
T7 |
1 |
|
T8 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3360 |
1 |
|
|
T2 |
46 |
|
T7 |
6 |
|
T8 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
334993 |
1 |
|
|
T2 |
4484 |
|
T7 |
22 |
|
T8 |
3391 |
auto[1] |
539 |
1 |
|
|
T9 |
75 |
|
T10 |
21 |
|
T11 |
18 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
176170 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
117667 |
1 |
|
|
T2 |
122 |
|
T8 |
80 |
|
T21 |
123 |
seven_bytes |
6087 |
1 |
|
|
T2 |
125 |
|
T8 |
89 |
|
T18 |
114 |
six_bytes |
5977 |
1 |
|
|
T2 |
133 |
|
T7 |
1 |
|
T8 |
98 |
five_bytes |
5894 |
1 |
|
|
T2 |
113 |
|
T8 |
83 |
|
T18 |
116 |
four_bytes |
5872 |
1 |
|
|
T2 |
121 |
|
T8 |
87 |
|
T18 |
109 |
three_bytes |
5850 |
1 |
|
|
T2 |
110 |
|
T7 |
1 |
|
T8 |
86 |
two_bytes |
6052 |
1 |
|
|
T2 |
125 |
|
T8 |
91 |
|
T18 |
117 |
one_byte |
5963 |
1 |
|
|
T2 |
113 |
|
T7 |
1 |
|
T8 |
87 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329102 |
1 |
|
|
T2 |
4426 |
|
T7 |
20 |
|
T8 |
3345 |
auto[1] |
6430 |
1 |
|
|
T2 |
58 |
|
T7 |
2 |
|
T8 |
46 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335532 |
1 |
|
|
T2 |
4484 |
|
T7 |
22 |
|
T8 |
3391 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335512 |
1 |
|
|
T2 |
4484 |
|
T7 |
22 |
|
T8 |
3389 |
auto[1] |
20 |
1 |
|
|
T8 |
2 |
|
T17 |
1 |
|
T71 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2191 |
1 |
|
|
T2 |
9 |
|
T8 |
7 |
|
T21 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6430 |
1 |
|
|
T2 |
58 |
|
T7 |
2 |
|
T8 |
46 |