Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

264565484

1

T1

141380

T2

43564

T3

274802

full_word

185840576

1

T1

911706

T2

66079

T3

175816

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450405780	1			T1	232551		T2	109643		T3	450618
auto[TlIntgErrCmd]	100	1			T116	3		T117	5		T118	5
auto[TlIntgErrData]	90	1			T116	3		T117	4		T118	6
auto[TlIntgErrBoth]	90	1			T116	4		T117	1		T118	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231877118

1

T1

117989

T2

73842

T3

228173

auto[1]

218528942

1

T1

114561

T2

35801

T3

222445

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160113636	1			T1	844317		T2	28051		T3	165005
auto[TlIntgErrNone]	partial	auto[1]	104451596	1			T1	569487		T2	15513		T3	109797
auto[TlIntgErrNone]	full_word	auto[0]	71763372	1			T1	335578		T2	45791		T3	63168
auto[TlIntgErrNone]	full_word	auto[1]	114077176	1			T1	576128		T2	20288		T3	112648
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T117	1		T118	3		T163	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T116	2		T117	4		T118	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T116	1		T165	1		T166	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T118	1		T163	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T116	2		T117	1		T118	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T116	1		T117	3		T118	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T167	1		T166	1		T168	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T169	1		T167	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T118	4		T143	1		T163	5
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T116	3		T117	1		T118	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T167	1		T171	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T116	1		T165	2		T164	1