Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	737244	0	0
entropy_period_rd_A	2147483647	1620	0	0
intr_enable_rd_A	2147483647	2499	0	0
prefix_0_rd_A	2147483647	1686	0	0
prefix_10_rd_A	2147483647	1776	0	0
prefix_1_rd_A	2147483647	1774	0	0
prefix_2_rd_A	2147483647	1732	0	0
prefix_3_rd_A	2147483647	1896	0	0
prefix_4_rd_A	2147483647	1729	0	0
prefix_5_rd_A	2147483647	1592	0	0
prefix_6_rd_A	2147483647	1748	0	0
prefix_7_rd_A	2147483647	1755	0	0
prefix_8_rd_A	2147483647	1792	0	0
prefix_9_rd_A	2147483647	1718	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	737244	0	0
T24	717129	82406	0	0
T53	0	102882	0	0
T54	0	10631	0	0
T72	865744	0	0	0
T122	0	39406	0	0
T123	0	69052	0	0
T124	0	30432	0	0
T125	0	19748	0	0
T126	0	14331	0	0
T127	0	55016	0	0
T128	0	8837	0	0
T129	286497	0	0	0
T130	188996	0	0	0
T131	993173	0	0	0
T132	262734	0	0	0
T133	426439	0	0	0
T134	29565	0	0	0
T135	160121	0	0	0
T136	159648	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1620	0	0
T87	2409	6	0	0
T90	6175	34	0	0
T91	11506	28	0	0
T142	10502	21	0	0
T143	10803	27	0	0
T144	4830	4	0	0
T145	14712	51	0	0
T146	9990	37	0	0
T147	4644	15	0	0
T148	6800	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2499	0	0
T87	2409	4	0	0
T90	6175	53	0	0
T91	11506	58	0	0
T119	972	20	0	0
T142	10502	56	0	0
T143	10803	32	0	0
T144	4830	1	0	0
T149	1130	10	0	0
T150	1501	23	0	0
T151	1133	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1686	0	0
T87	2409	7	0	0
T90	6175	33	0	0
T91	11506	28	0	0
T142	10502	13	0	0
T143	10803	27	0	0
T144	4830	1	0	0
T145	14712	36	0	0
T146	9990	26	0	0
T147	4644	6	0	0
T148	6800	23	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1776	0	0
T87	2409	3	0	0
T90	6175	24	0	0
T91	11506	45	0	0
T92	8699	37	0	0
T142	10502	32	0	0
T143	10803	36	0	0
T144	4830	11	0	0
T145	14712	36	0	0
T146	9990	5	0	0
T148	6800	41	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T87	2409	4	0	0
T90	6175	38	0	0
T91	11506	27	0	0
T142	10502	36	0	0
T143	10803	31	0	0
T145	14712	37	0	0
T146	9990	11	0	0
T147	4644	11	0	0
T148	6800	14	0	0
T152	5965	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1732	0	0
T87	2409	3	0	0
T90	6175	22	0	0
T91	11506	32	0	0
T92	8699	26	0	0
T142	10502	44	0	0
T143	10803	17	0	0
T145	14712	39	0	0
T146	9990	10	0	0
T147	4644	8	0	0
T148	6800	7	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1896	0	0
T90	6175	23	0	0
T91	11506	21	0	0
T92	8699	32	0	0
T142	10502	59	0	0
T143	10803	11	0	0
T144	4830	14	0	0
T145	14712	62	0	0
T146	9990	14	0	0
T147	4644	13	0	0
T148	6800	20	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1729	0	0
T87	2409	1	0	0
T90	6175	34	0	0
T91	11506	24	0	0
T142	10502	49	0	0
T143	10803	25	0	0
T144	4830	1	0	0
T145	14712	54	0	0
T146	9990	22	0	0
T147	4644	13	0	0
T148	6800	52	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1592	0	0
T90	6175	21	0	0
T91	11506	21	0	0
T92	8699	25	0	0
T142	10502	76	0	0
T143	10803	19	0	0
T144	4830	11	0	0
T145	14712	39	0	0
T146	9990	22	0	0
T147	4644	11	0	0
T148	6800	23	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1748	0	0
T87	2409	5	0	0
T90	6175	29	0	0
T91	11506	25	0	0
T142	10502	26	0	0
T143	10803	29	0	0
T144	4830	2	0	0
T145	14712	37	0	0
T146	9990	10	0	0
T147	4644	6	0	0
T148	6800	34	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1755	0	0
T87	2409	2	0	0
T90	6175	36	0	0
T91	11506	14	0	0
T142	10502	75	0	0
T143	10803	39	0	0
T144	4830	12	0	0
T145	14712	52	0	0
T146	9990	10	0	0
T147	4644	13	0	0
T148	6800	41	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1792	0	0
T90	6175	33	0	0
T91	11506	22	0	0
T92	8699	30	0	0
T142	10502	44	0	0
T143	10803	36	0	0
T144	4830	2	0	0
T145	14712	26	0	0
T146	9990	64	0	0
T147	4644	2	0	0
T148	6800	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1718	0	0
T87	2409	5	0	0
T90	6175	34	0	0
T91	11506	15	0	0
T142	10502	32	0	0
T143	10803	12	0	0
T144	4830	6	0	0
T145	14712	41	0	0
T146	9990	11	0	0
T147	4644	4	0	0
T148	6800	30	0	0