Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170165 |
1 |
|
|
T2 |
169 |
|
T3 |
588 |
|
T7 |
106 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87684 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61415 |
1 |
|
|
T2 |
166 |
|
T3 |
578 |
|
T7 |
105 |
seven_bytes |
2965 |
1 |
|
|
T17 |
7 |
|
T18 |
31 |
|
T34 |
12 |
six_bytes |
2992 |
1 |
|
|
T17 |
8 |
|
T18 |
41 |
|
T34 |
11 |
five_bytes |
3021 |
1 |
|
|
T17 |
9 |
|
T18 |
31 |
|
T34 |
17 |
four_bytes |
3072 |
1 |
|
|
T17 |
12 |
|
T18 |
40 |
|
T34 |
15 |
three_bytes |
2942 |
1 |
|
|
T17 |
10 |
|
T18 |
30 |
|
T34 |
14 |
two_bytes |
3111 |
1 |
|
|
T17 |
3 |
|
T18 |
38 |
|
T34 |
12 |
one_byte |
2963 |
1 |
|
|
T17 |
5 |
|
T18 |
26 |
|
T34 |
13 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
166887 |
1 |
|
|
T2 |
163 |
|
T3 |
568 |
|
T7 |
104 |
auto[1] |
3278 |
1 |
|
|
T2 |
6 |
|
T3 |
20 |
|
T7 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170165 |
1 |
|
|
T2 |
169 |
|
T3 |
588 |
|
T7 |
106 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170151 |
1 |
|
|
T2 |
169 |
|
T3 |
587 |
|
T7 |
106 |
auto[1] |
14 |
1 |
|
|
T3 |
1 |
|
T151 |
1 |
|
T136 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1125 |
1 |
|
|
T2 |
3 |
|
T3 |
10 |
|
T7 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3278 |
1 |
|
|
T2 |
6 |
|
T3 |
20 |
|
T7 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164211 |
1 |
|
|
T2 |
278 |
|
T3 |
738 |
|
T7 |
154 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86133 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57445 |
1 |
|
|
T2 |
186 |
|
T3 |
724 |
|
T7 |
151 |
seven_bytes |
2958 |
1 |
|
|
T17 |
10 |
|
T18 |
34 |
|
T34 |
8 |
six_bytes |
2963 |
1 |
|
|
T2 |
1 |
|
T17 |
10 |
|
T18 |
42 |
five_bytes |
2946 |
1 |
|
|
T2 |
2 |
|
T17 |
14 |
|
T18 |
40 |
four_bytes |
3039 |
1 |
|
|
T2 |
1 |
|
T17 |
14 |
|
T18 |
37 |
three_bytes |
2931 |
1 |
|
|
T2 |
2 |
|
T17 |
4 |
|
T18 |
29 |
two_bytes |
2859 |
1 |
|
|
T2 |
2 |
|
T17 |
7 |
|
T18 |
51 |
one_byte |
2937 |
1 |
|
|
T2 |
4 |
|
T17 |
8 |
|
T18 |
49 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161045 |
1 |
|
|
T2 |
270 |
|
T3 |
710 |
|
T7 |
148 |
auto[1] |
3166 |
1 |
|
|
T2 |
8 |
|
T3 |
28 |
|
T7 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164211 |
1 |
|
|
T2 |
278 |
|
T3 |
738 |
|
T7 |
154 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164202 |
1 |
|
|
T2 |
278 |
|
T3 |
738 |
|
T7 |
154 |
auto[1] |
9 |
1 |
|
|
T152 |
1 |
|
T153 |
1 |
|
T154 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1074 |
1 |
|
|
T2 |
4 |
|
T3 |
14 |
|
T7 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3166 |
1 |
|
|
T2 |
8 |
|
T3 |
28 |
|
T7 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337551 |
1 |
|
|
T2 |
1609 |
|
T3 |
1243 |
|
T7 |
662 |
auto[1] |
489 |
1 |
|
|
T5 |
87 |
|
T8 |
22 |
|
T9 |
43 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
175344 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
121329 |
1 |
|
|
T2 |
468 |
|
T3 |
1223 |
|
T7 |
650 |
seven_bytes |
6109 |
1 |
|
|
T2 |
35 |
|
T17 |
16 |
|
T18 |
110 |
six_bytes |
5914 |
1 |
|
|
T2 |
45 |
|
T17 |
13 |
|
T18 |
79 |
five_bytes |
5899 |
1 |
|
|
T2 |
25 |
|
T17 |
12 |
|
T18 |
66 |
four_bytes |
5810 |
1 |
|
|
T2 |
38 |
|
T17 |
12 |
|
T18 |
75 |
three_bytes |
5835 |
1 |
|
|
T2 |
31 |
|
T17 |
15 |
|
T18 |
81 |
two_bytes |
5851 |
1 |
|
|
T2 |
37 |
|
T17 |
7 |
|
T18 |
74 |
one_byte |
5949 |
1 |
|
|
T2 |
36 |
|
T17 |
13 |
|
T18 |
88 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
331526 |
1 |
|
|
T2 |
1583 |
|
T3 |
1203 |
|
T7 |
638 |
auto[1] |
6514 |
1 |
|
|
T2 |
26 |
|
T3 |
40 |
|
T7 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338040 |
1 |
|
|
T2 |
1609 |
|
T3 |
1243 |
|
T7 |
662 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338017 |
1 |
|
|
T2 |
1609 |
|
T3 |
1243 |
|
T7 |
662 |
auto[1] |
23 |
1 |
|
|
T50 |
2 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2264 |
1 |
|
|
T2 |
7 |
|
T3 |
20 |
|
T7 |
12 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6514 |
1 |
|
|
T2 |
26 |
|
T3 |
40 |
|
T7 |
24 |