Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259908549

1

T1

10

T2

431413

T3

56632

full_word

183049764

1

T1

2

T2

261042

T3

80151

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	442958023	1			T1	12		T2	692455		T3	136783
auto[TlIntgErrCmd]	107	1			T111	3		T112	5		T113	3
auto[TlIntgErrData]	94	1			T111	4		T112	1		T113	4
auto[TlIntgErrBoth]	89	1			T111	3		T112	4		T113	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228969747

1

T1

1

T2

307551

T3

90402

auto[1]

213988566

1

T1

11

T2

384904

T3

46381

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158029451	1			T1	1		T2	203161		T3	36379
auto[TlIntgErrNone]	partial	auto[1]	101878830	1			T1	9		T2	228252		T3	20253
auto[TlIntgErrNone]	full_word	auto[0]	70940155	1			T2	104390		T3	54023		T7	16757
auto[TlIntgErrNone]	full_word	auto[1]	112109587	1			T1	2		T2	156652		T3	26128
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T111	1		T112	3		T113	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T111	2		T112	2		T155	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T162	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T163	1		T161	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T111	3		T112	1		T113	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T111	1		T113	1		T156	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T162	1		T157	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T156	1		T162	1		T157	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T111	2		T112	4		T113	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T111	1		T113	2		T156	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T156	3		T157	1		T161	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T161	1		T165	1		T159	1