Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259019217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185568626

1

T1

472808

T2

342774

T3

68

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230373934	1			T1	592874		T2	448183		T3	33
values[0x0]	102891824	1			T1	259836		T2	214548		T3	37
values[0x1]	111322085	1			T1	277554		T2	231550		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201162565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243425278

1

T1

615078

T2

462749

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2039907	1			T1	502		T2	3574		T16	9141
valid_sources[0x01]	1353229	1			T1	502		T2	3571		T3	1
valid_sources[0x02]	1356005	1			T1	447		T2	3400		T16	9309
valid_sources[0x03]	1357791	1			T1	489		T2	3460		T16	9190
valid_sources[0x04]	1485355	1			T1	522		T2	3560		T16	9154
valid_sources[0x05]	1351858	1			T1	474		T2	3576		T16	9189
valid_sources[0x06]	1364810	1			T1	454		T2	3382		T16	9041
valid_sources[0x07]	1354368	1			T1	486		T2	3464		T16	9102
valid_sources[0x08]	1354810	1			T1	503		T2	3419		T16	9224
valid_sources[0x09]	1364532	1			T1	494		T2	3400		T16	9108
valid_sources[0x0a]	2255048	1			T1	477		T2	3390		T16	9010
valid_sources[0x0b]	1357571	1			T1	484		T2	3581		T3	1
valid_sources[0x0c]	1998200	1			T1	518		T2	3332		T16	9233
valid_sources[0x0d]	1433388	1			T1	482		T2	3484		T16	9242
valid_sources[0x0e]	1357341	1			T1	468		T2	3430		T3	1
valid_sources[0x0f]	3427412	1			T1	509		T2	3541		T3	2
valid_sources[0x10]	1501794	1			T1	488		T2	3501		T16	9160
valid_sources[0x11]	1365743	1			T1	472		T2	3595		T3	1
valid_sources[0x12]	1358254	1			T1	515		T2	3611		T3	2
valid_sources[0x13]	1354469	1			T1	516		T2	3494		T16	9172
valid_sources[0x14]	2207436	1			T1	505		T2	3682		T16	8979
valid_sources[0x15]	1856246	1			T1	509		T2	3488		T16	9131
valid_sources[0x16]	1361293	1			T1	508		T2	3552		T16	9062
valid_sources[0x17]	1358317	1			T1	521		T2	3555		T3	2
valid_sources[0x18]	1379637	1			T1	475		T2	3456		T16	9229
valid_sources[0x19]	1398945	1			T1	450		T2	3594		T3	1
valid_sources[0x1a]	1379578	1			T1	505		T2	3517		T16	9282
valid_sources[0x1b]	1355098	1			T1	500		T2	3437		T16	9266
valid_sources[0x1c]	1352090	1			T1	481		T2	3534		T16	9054
valid_sources[0x1d]	1359557	1			T1	509		T2	3314		T16	9171
valid_sources[0x1e]	1352830	1			T1	495		T2	3447		T16	9160
valid_sources[0x1f]	1379644	1			T1	478		T2	3583		T16	9177
valid_sources[0x20]	1364052	1			T1	526		T2	3566		T16	9085
valid_sources[0x21]	1355491	1			T1	481		T2	3498		T16	9286
valid_sources[0x22]	1361619	1			T1	494		T2	3488		T16	9129
valid_sources[0x23]	1383886	1			T1	483		T2	3414		T16	9183
valid_sources[0x24]	1357377	1			T1	494		T2	3562		T3	3
valid_sources[0x25]	1357381	1			T1	465		T2	3529		T3	1
valid_sources[0x26]	1356204	1			T1	474		T2	3567		T16	9245
valid_sources[0x27]	1954270	1			T1	542		T2	3450		T16	9061
valid_sources[0x28]	1446647	1			T1	474		T2	3524		T16	9200
valid_sources[0x29]	1365502	1			T1	502		T2	3595		T16	9067
valid_sources[0x2a]	1468572	1			T1	517		T2	3499		T3	2
valid_sources[0x2b]	4650164	1			T1	494		T2	3376		T16	9233
valid_sources[0x2c]	1359069	1			T1	510		T2	3457		T16	9236
valid_sources[0x2d]	1366720	1			T1	492		T2	3415		T16	9320
valid_sources[0x2e]	1361147	1			T1	481		T2	3398		T16	9008
valid_sources[0x2f]	1811377	1			T1	462		T2	3543		T3	3
valid_sources[0x30]	1380206	1			T1	490		T2	3441		T16	9261
valid_sources[0x31]	1366219	1			T1	490		T2	3413		T16	9197
valid_sources[0x32]	2085983	1			T1	466		T2	3516		T16	9205
valid_sources[0x33]	1358744	1			T1	461		T2	3505		T16	8971
valid_sources[0x34]	1394990	1			T1	511		T2	3425		T16	9151
valid_sources[0x35]	1363819	1			T1	515		T2	3468		T16	9151
valid_sources[0x36]	1349969	1			T1	521		T2	3655		T3	3
valid_sources[0x37]	1359815	1			T1	545		T2	3575		T16	9171
valid_sources[0x38]	1357686	1			T1	451		T2	3470		T3	1
valid_sources[0x39]	3449459	1			T1	535		T2	3539		T3	1
valid_sources[0x3a]	1415657	1			T1	479		T2	3467		T16	9102
valid_sources[0x3b]	2093976	1			T1	475		T2	3361		T16	9252
valid_sources[0x3c]	1488871	1			T1	482		T2	3562		T16	9288
valid_sources[0x3d]	2261085	1			T1	456		T2	3573		T16	9267
valid_sources[0x3e]	1359567	1			T1	498		T2	3494		T16	9263
valid_sources[0x3f]	1356754	1			T1	522		T2	3585		T16	9175
valid_sources[0x40]	1353694	1			T1	494		T2	3338		T16	9093
valid_sources[0x41]	1357899	1			T1	462		T2	3501		T16	9223
valid_sources[0x42]	1358994	1			T1	498		T2	3594		T16	9064
valid_sources[0x43]	3639828	1			T1	466		T2	3643		T16	9076
valid_sources[0x44]	1353995	1			T1	481		T2	3487		T16	9011
valid_sources[0x45]	1364070	1			T1	483		T2	3460		T16	9368
valid_sources[0x46]	1813422	1			T1	532		T2	3584		T16	9190
valid_sources[0x47]	1384862	1			T1	508		T2	3408		T16	9207
valid_sources[0x48]	2020980	1			T1	483		T2	3570		T16	9177
valid_sources[0x49]	1355966	1			T1	472		T2	3490		T3	3
valid_sources[0x4a]	2360974	1			T1	100400		T2	3547		T16	9339
valid_sources[0x4b]	1530596	1			T1	491		T2	3427		T16	9048
valid_sources[0x4c]	2138419	1			T1	518		T2	3605		T16	9188
valid_sources[0x4d]	3569092	1			T1	490		T2	3485		T3	1
valid_sources[0x4e]	1357028	1			T1	497		T2	3451		T16	9244
valid_sources[0x4f]	1535949	1			T1	465		T2	3500		T16	9138
valid_sources[0x50]	1358119	1			T1	488		T2	3475		T16	9193
valid_sources[0x51]	1689016	1			T1	507		T2	3364		T16	9123
valid_sources[0x52]	1354124	1			T1	511		T2	3364		T16	9176
valid_sources[0x53]	1441225	1			T1	463		T2	3412		T16	9092
valid_sources[0x54]	1359620	1			T1	463		T2	3589		T16	9120
valid_sources[0x55]	1367097	1			T1	486		T2	3506		T16	9280
valid_sources[0x56]	1360584	1			T1	500		T2	3454		T16	9022
valid_sources[0x57]	1356308	1			T1	499		T2	3307		T16	9180
valid_sources[0x58]	1356038	1			T1	519		T2	3418		T16	8984
valid_sources[0x59]	1510987	1			T1	496		T2	3405		T16	9043
valid_sources[0x5a]	2783204	1			T1	501		T2	3568		T3	2
valid_sources[0x5b]	1351247	1			T1	519		T2	3441		T3	1
valid_sources[0x5c]	1360175	1			T1	494		T2	3404		T16	9234
valid_sources[0x5d]	2253308	1			T1	486		T2	3434		T16	9200
valid_sources[0x5e]	3346124	1			T1	456		T2	3572		T3	2
valid_sources[0x5f]	1434747	1			T1	508		T2	3465		T3	1
valid_sources[0x60]	1544476	1			T1	540		T2	3519		T3	1
valid_sources[0x61]	1357754	1			T1	502		T2	3483		T16	9155
valid_sources[0x62]	3641996	1			T1	502		T2	3465		T16	9135
valid_sources[0x63]	3726257	1			T1	520		T2	3593		T3	1
valid_sources[0x64]	3721956	1			T1	516		T2	3489		T16	9213
valid_sources[0x65]	3721496	1			T1	500		T2	3649		T3	1
valid_sources[0x66]	1362231	1			T1	525		T2	3565		T16	9170
valid_sources[0x67]	1352112	1			T1	530		T2	3363		T3	1
valid_sources[0x68]	1368417	1			T1	467		T2	3556		T16	9158
valid_sources[0x69]	1357853	1			T1	455		T2	3571		T3	2
valid_sources[0x6a]	1364082	1			T1	488		T2	3517		T16	9111
valid_sources[0x6b]	1777397	1			T1	517		T2	3369		T3	1
valid_sources[0x6c]	1362491	1			T1	518		T2	3553		T16	9248
valid_sources[0x6d]	1383391	1			T1	491		T2	3597		T3	2
valid_sources[0x6e]	1359904	1			T1	507		T2	3374		T16	9251
valid_sources[0x6f]	2271874	1			T1	515		T2	3514		T3	1
valid_sources[0x70]	1360252	1			T1	508		T2	3490		T3	1
valid_sources[0x71]	1494853	1			T1	508		T2	3444		T16	9258
valid_sources[0x72]	1355392	1			T1	501		T2	3456		T16	9144
valid_sources[0x73]	2222533	1			T1	529		T2	3465		T16	9162
valid_sources[0x74]	1447783	1			T1	476		T2	3476		T16	9239
valid_sources[0x75]	2003166	1			T1	513		T2	3482		T3	2
valid_sources[0x76]	1489640	1			T1	527		T2	3532		T16	9283
valid_sources[0x77]	1375503	1			T1	526		T2	3541		T16	9116
valid_sources[0x78]	1439887	1			T1	490		T2	3401		T3	1
valid_sources[0x79]	1351989	1			T1	507		T2	3461		T16	9217
valid_sources[0x7a]	3335927	1			T1	527		T2	3502		T16	9103
valid_sources[0x7b]	1372842	1			T1	486		T2	3356		T16	9444
valid_sources[0x7c]	1354080	1			T1	522		T2	3529		T16	9244
valid_sources[0x7d]	1367721	1			T1	491		T2	3634		T3	1
valid_sources[0x7e]	1359521	1			T1	481		T2	3582		T3	1
valid_sources[0x7f]	3086924	1			T1	446		T2	3583		T3	1
valid_sources[0x80]	1357071	1			T1	477		T2	3438		T16	9016

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71593472

1

T1

189983

T2

116523

T3

24

values[0x0]

all_enables

biggest_size

61170781

1

T1

152938

T2

122603

T3

25

values[0x1]

all_enables

biggest_size

52804373

1

T1

129887

T2

103648

T3

19