Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263105319

1

T1

657456

T2

551507

T3

36

full_word

185825913

1

T1

472808

T2

342774

T3

68

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448930942	1			T1	113026		T2	894281		T3	104
auto[TlIntgErrCmd]	105	1			T110	3		T111	8		T112	6
auto[TlIntgErrData]	109	1			T110	6		T111	7		T112	8
auto[TlIntgErrBoth]	76	1			T110	1		T111	5		T112	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231168681

1

T1

592874

T2

448183

T3

33

auto[1]

217762551

1

T1

537390

T2

446098

T3

71

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159510372	1			T1	402891		T2	331660		T3	9
auto[TlIntgErrNone]	partial	auto[1]	103594677	1			T1	254565		T2	219847		T3	27
auto[TlIntgErrNone]	full_word	auto[0]	71658183	1			T1	189983		T2	116523		T3	24
auto[TlIntgErrNone]	full_word	auto[1]	114167710	1			T1	282825		T2	226251		T3	44
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T111	3		T159	1		T158	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T110	3		T111	4		T112	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T111	1		T160	1		T161	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T162	1		T163	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T110	2		T111	4		T112	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T110	3		T111	2		T112	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T110	1		T112	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T111	1		T159	1		T165	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T111	1		T112	3		T158	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T110	1		T111	3		T112	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T111	1		T164	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T112	1		T166	2		-	-