Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.89	99.41	88.37		80.95	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	95.59	99.41	88.37		94.44	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.59	99.41	88.37		94.44	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.34	99.45	88.37	100.00	94.44	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	97.56	88.89		100.00	93.33	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	680	17	17	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
538	1	1
558	1	1
559	1	1
560	1	1
561	1	1
578	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	1	1
683	1	1
686	1	1
687	1	1
690	1	1
691	1	1
694	1	1
695	1	1
698	1	1
699	1	1
702	1	1
703	1	1
706	1	1
707	1	1
710	1	1
711	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T33

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T33

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T16
1	0	1	Covered	T7,T17,T10
1	1	0	Covered	T1,T2,T16
1	1	1	Covered	T1,T2,T16

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	17	80.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T16
StMessageWait	383	Covered	T1,T2,T16
StPad	389	Covered	T1,T2,T16
StPad01	427	Covered	T1,T2,T16
StPadFlush	435	Covered	T1,T2,T16
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T2,T16
StPrefix	328	Covered	T1,T33,T4
StPrefixWait	348	Covered	T1,T33,T4
StTerminalError	495	Covered	T13,T14,T15

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	383	Covered	T1,T2,T16
StMessage->StPad	389	Covered	T1,T2,T16
StMessage->StTerminalError	495	Covered	T15,T27,T47
StMessageWait->StMessage	403	Covered	T1,T2,T16
StMessageWait->StTerminalError	495	Covered	T13,T26,T48
StPad->StPad01	427	Covered	T1,T2,T16
StPad->StPadRun	421	Covered	T1,T2,T16
StPad->StTerminalError	495	Not Covered
StPad01->StPadFlush	452	Covered	T1,T2,T16
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Covered	T1,T2,T16
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T2,T16
StPadIdle->StPrefix	328	Covered	T1,T33,T4
StPadIdle->StTerminalError	495	Covered	T28,T29,T30
StPadRun->StPadFlush	435	Covered	T1,T2,T16
StPadRun->StTerminalError	495	Not Covered
StPrefix->StPrefixWait	348	Covered	T1,T33,T4
StPrefix->StTerminalError	495	Covered	T66,T67
StPrefixWait->StMessage	364	Covered	T1,T33,T4
StPrefixWait->StTerminalError	495	Covered	T14,T53,T54

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	680	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T2,T35
L256	Covered	T1,T2,T3
L384	Covered	T4,T7,T37
L512	Covered	T1,T8,T64
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T16
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T16
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T16
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T16
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T16
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T16
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T16
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T16
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T16
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T16
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T16
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T16
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T30,T32

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T3,T16
CShake	Covered	T1,T3,T33
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T16
MuxPrefix	Covered	T1,T33,T4
MuxFuncPad	Covered	T1,T2,T16
MuxZeroEnd	Covered	T1,T2,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T16
MuxPrefix	Covered	T1,T33,T4
MuxFuncPad	Covered	T1,T2,T16
MuxZeroEnd	Covered	T1,T2,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T16
MuxPrefix	Covered	T1,T33,T4
MuxFuncPad	Covered	T1,T2,T16
MuxZeroEnd	Covered	T1,T2,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	680	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T2,T16
7'b0000011	Covered	T1,T2,T16
7'b0000111	Covered	T1,T2,T16
7'b0001111	Covered	T1,T2,T16
7'b0011111	Covered	T1,T2,T16
7'b0111111	Covered	T1,T2,T16
7'b1111111	Covered	T1,T2,T16
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	345051	0	0
AlwaysPartialMsgBuf_M	2147483647	196953	0	0
CompleteBlockWhenProcess_A	2147483647	332944	0	0
DoneCondition_M	2147483647	345046	0	0
DonePulse_A	2147483647	345046	0	0
KeccakAddrInRange_A	2147483647	52945128	0	0
KeccakRunPulse_A	2147483647	3065744	0	0
MessageCondition_M	2147483647	48219848	0	0
ModeStableDuringOp_M	2147483647	34247	0	0
MsgReadyCondition_A	2147483647	2053952272	0	0
MsgWidthidth_A	1025	1025	0	0
NoPartialMsgFifo_M	2147483647	48022895	0	0
Pad01NotAttheEndOfBlock_A	2147483647	334367	0	0
PartialEndOfMsg_M	2147483647	196953	0	0
PrefixLessThanBlock_A	1025	1025	0	0
ProcessCondition_M	2147483647	345070	0	0
ProcessPulse_A	2147483647	345070	0	0
StartCondition_M	2147483647	345124	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	345124	0	0
StrengthStableDuringOp_M	2147483647	41280	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345051	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196953	0	0
T1	985024	151	0	0
T2	224130	340	0	0
T3	2357	0	0	0
T4	112135	0	0	0
T7	198548	134	0	0
T8	0	237	0	0
T9	0	87	0	0
T16	234675	1058	0	0
T33	14205	9	0	0
T34	722302	48	0	0
T35	654242	340	0	0
T36	1894	0	0	0
T37	0	45	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332944	0	0
T1	985024	163	0	0
T2	224130	372	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	152	0	0
T8	0	251	0	0
T16	234675	2283	0	0
T33	14205	9	0	0
T34	722302	47	0	0
T35	654242	372	0	0
T36	1894	0	0	0
T37	0	56	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345046	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345046	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52945128	0	0
T1	985024	123560	0	0
T2	224130	99756	0	0
T3	2357	0	0	0
T4	112135	612	0	0
T7	198548	59172	0	0
T8	0	33381	0	0
T16	234675	276087	0	0
T33	14205	607	0	0
T34	722302	35466	0	0
T35	654242	99756	0	0
T36	1894	0	0	0
T37	0	43024	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3065744	0	0
T1	985024	6572	0	0
T2	224130	5542	0	0
T3	2357	0	0	0
T4	112135	36	0	0
T7	198548	3228	0	0
T8	0	1837	0	0
T16	234675	13147	0	0
T33	14205	31	0	0
T34	722302	1876	0	0
T35	654242	5542	0	0
T36	1894	0	0	0
T37	0	2276	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48219848	0	0
T1	985024	119139	0	0
T2	224130	96112	0	0
T3	2357	0	0	0
T4	112135	204	0	0
T7	198548	55219	0	0
T8	0	27227	0	0
T16	234675	241576	0	0
T33	14205	286	0	0
T34	722302	34155	0	0
T35	654242	96112	0	0
T36	1894	0	0	0
T37	0	41692	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34247	0	0
T1	985024	56	0	0
T2	224130	0	0	0
T3	2357	4	0	0
T4	112135	26	0	0
T7	198548	120	0	0
T8	0	201	0	0
T9	0	54	0	0
T16	234675	1	0	0
T33	14205	1	0	0
T34	722302	15	0	0
T35	654242	0	0	0
T36	1894	0	0	0
T37	0	27	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053952272	0	0
T1	985024	844556	0	0
T2	224130	126548	0	0
T3	2357	0	0	0
T4	112135	98711	0	0
T7	198548	109012	0	0
T8	0	183564	0	0
T16	234675	194653	0	0
T33	14205	957	0	0
T34	722302	354387	0	0
T35	654242	574812	0	0
T36	1894	0	0	0
T37	0	435803	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48022895	0	0
T1	985024	118988	0	0
T2	224130	95772	0	0
T3	2357	0	0	0
T4	112135	204	0	0
T7	198548	55085	0	0
T8	0	26990	0	0
T16	234675	240518	0	0
T33	14205	277	0	0
T34	722302	34107	0	0
T35	654242	95772	0	0
T36	1894	0	0	0
T37	0	41647	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334367	0	0
T1	985024	165	0	0
T2	224130	374	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	155	0	0
T8	0	253	0	0
T16	234675	2289	0	0
T33	14205	9	0	0
T34	722302	47	0	0
T35	654242	374	0	0
T36	1894	0	0	0
T37	0	56	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196953	0	0
T1	985024	151	0	0
T2	224130	340	0	0
T3	2357	0	0	0
T4	112135	0	0	0
T7	198548	134	0	0
T8	0	237	0	0
T9	0	87	0	0
T16	234675	1058	0	0
T33	14205	9	0	0
T34	722302	48	0	0
T35	654242	340	0	0
T36	1894	0	0	0
T37	0	45	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345070	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345070	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345124	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	985024	985017	0	0
T2	224130	224122	0	0
T3	2357	2307	0	0
T4	112135	112054	0	0
T7	198548	198506	0	0
T16	234675	234675	0	0
T33	14205	14148	0	0
T34	722302	722219	0	0
T35	654242	654234	0	0
T36	1894	1834	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345124	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41280	0	0
T1	985024	95	0	0
T2	224130	2	0	0
T3	2357	4	0	0
T4	112135	22	0	0
T7	198548	122	0	0
T16	234675	1	0	0
T33	14205	2	0	0
T34	722302	30	0	0
T35	654242	2	0	0
T36	1894	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	985024	985017	0	0
T2	224130	224122	0	0
T3	2357	2307	0	0
T4	112135	112054	0	0
T7	198548	198506	0	0
T16	234675	234675	0	0
T33	14205	14148	0	0
T34	722302	722219	0	0
T35	654242	654234	0	0
T36	1894	1834	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33503503	0
StMessageFeed_C	2147483647	2056979063	0
StPadSendMsg_C	2147483647	3844786	0
StPad_C	2147483647	334367	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33503503	0
T1	985024	16781	0
T2	224130	37842	0
T3	2357	0	0
T4	112135	1164	0
T7	198548	15520	0
T8	0	26384	0
T16	234675	226689	0
T33	14205	873	0
T34	722302	5044	0
T35	654242	37857	0
T36	1894	0	0
T37	0	5529	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2056979063	0
T1	985024	845200	0
T2	224130	127102	0
T3	2357	0	0
T4	112135	98735	0
T7	198548	109323	0
T8	0	183729	0
T16	234675	194784	0
T33	14205	979	0
T34	722302	356219	0
T35	654242	575366	0
T36	1894	0	0
T37	0	438040	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3844786	0
T1	985024	1781	0
T2	224130	3594	0
T3	2357	0	0
T4	112135	192	0
T7	198548	1687	0
T8	0	2555	0
T16	234675	33232	0
T33	14205	144	0
T34	722302	471	0
T35	654242	3594	0
T36	1894	0	0
T37	0	565	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	334367	0
T1	985024	165	0
T2	224130	374	0
T3	2357	0	0
T4	112135	12	0
T7	198548	155	0
T8	0	253	0
T16	234675	2289	0
T33	14205	9	0
T34	722302	47	0
T35	654242	374	0
T36	1894	0	0
T37	0	56	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		170	169	99.41
ALWAYS	157	6	6	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	267	6	6	100.00
ALWAYS	279	3	3	100.00
CONT_ASSIGN	286	1	1	100.00
ALWAYS	293	3	3	100.00
ALWAYS	298	76	75	98.68
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
ALWAYS	558	4	4	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
ALWAYS	591	5	5	100.00
ALWAYS	603	5	5	100.00
ALWAYS	615	5	5	100.00
ALWAYS	664	10	10	100.00
ALWAYS	680	17	17	100.00
ALWAYS	779	6	6	100.00
ALWAYS	788	6	6	100.00
ALWAYS	798	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
209	1	1
213	1	1
236	1	1
242	1	1
247	1	1
257	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
272	1	1
			MISSING_ELSE
279	3	3
286	1	1
293	2	2
294	1	1
298	1	1
301	1	1
302	1	1
304	1	1
306	1	1
307	1	1
309	1	1
310	1	1
312	1	1
314	1	1
316	1	1
325	1	1
327	1	1
328	1	1
330	1	1
333	1	1
345	1	1
347	1	1
348	1	1
350	1	1
351	1	1
352	1	1
354	1	1
356	1	1
361	1	1
363	1	1
364	1	1
366	1	1
375	1	1
377	1	1
378	1	1
380	1	1
381	1	1
383	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
392	1	1
394	1	1
400	1	1
402	1	1
403	1	1
405	1	1
414	1	1
416	1	1
418	1	1
421	1	1
424	1	1
425	1	1
426	1	1
427	1	1
428	1	1
430	0	1
435	1	1
437	1	1
438	1	1
447	1	1
451	1	1
452	1	1
454	1	1
455	1	1
456	1	1
458	1	1
460	1	1
466	1	1
467	1	1
469	1	1
470	1	1
472	1	1
474	1	1
480	1	1
481	1	1
494	1	1
495	1	1
			MISSING_ELSE
509	1	1
520	1	1
538	1	1
558	1	1
559	1	1
560	1	1
561	1	1
578	1	1
588	1	1
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
669	1	1
671	1	1
672	1	1
673	1	1
674	1	1
			MISSING_ELSE
680	1	1
682	1	1
683	1	1
686	1	1
687	1	1
690	1	1
691	1	1
694	1	1
695	1	1
698	1	1
699	1	1
702	1	1
703	1	1
706	1	1
707	1	1
710	1	1
711	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
			MISSING_ELSE
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
			MISSING_ELSE
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T33

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T33

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T16
1	0	1	Covered	T7,T17,T10
1	1	0	Covered	T1,T2,T16
1	1	1	Covered	T1,T2,T16

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T16
0	1	Covered	T1,T2,T16
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T16

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	18	17	94.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Covered	T1,T2,T16
StMessageWait	383	Covered	T1,T2,T16
StPad	389	Covered	T1,T2,T16
StPad01	427	Covered	T1,T2,T16
StPadFlush	435	Covered	T1,T2,T16
StPadIdle	333	Covered	T1,T2,T3
StPadRun	421	Covered	T1,T2,T16
StPrefix	328	Covered	T1,T33,T4
StPrefixWait	348	Covered	T1,T33,T4
StTerminalError	495	Covered	T13,T14,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	383	Covered	T1,T2,T16
StMessage->StPad	389	Covered	T1,T2,T16
StMessage->StTerminalError	495	Covered	T15,T27,T47
StMessageWait->StMessage	403	Covered	T1,T2,T16
StMessageWait->StTerminalError	495	Covered	T13,T26,T48
StPad->StPad01	427	Covered	T1,T2,T16
StPad->StPadRun	421	Covered	T1,T2,T16
StPad->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	452	Covered	T1,T2,T16
StPad01->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadFlush->StPadIdle	470	Covered	T1,T2,T16
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Covered	T1,T2,T16
StPadIdle->StPrefix	328	Covered	T1,T33,T4
StPadIdle->StTerminalError	495	Covered	T28,T29,T30
StPadRun->StPadFlush	435	Covered	T1,T2,T16
StPadRun->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	348	Covered	T1,T33,T4
StPrefix->StTerminalError	495	Covered	T66,T67
StPrefixWait->StMessage	364	Covered	T1,T33,T4
StPrefixWait->StTerminalError	495	Covered	T14,T53,T54

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	213	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	242	2	2	100.00
TERNARY	286	2	2	100.00
TERNARY	588	2	2	100.00
CASE	157	6	5	83.33
IF	267	4	4	100.00
IF	279	2	2	100.00
IF	293	2	2	100.00
CASE	316	23	22	95.65
IF	494	2	2	100.00
CASE	558	4	3	75.00
CASE	591	5	5	100.00
CASE	603	5	5	100.00
CASE	615	5	5	100.00
IF	664	4	4	100.00
IF	779	4	4	100.00
IF	788	4	4	100.00
IF	798	4	4	100.00
CASE	680	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T1,T2,T3
L224	Covered	T1,T2,T35
L256	Covered	T1,T2,T3
L384	Covered	T4,T7,T37
L512	Covered	T1,T8,T64
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T33,T4
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T16
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T16
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T1,T2,T16
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T1,T2,T16
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T16
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T16
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T16
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T2,T16
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T16
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T16
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T16
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T16
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T16
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T30,T32

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T1,T2,T3
Shake	Covered	T1,T3,T16
CShake	Covered	T1,T3,T33
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T16
MuxPrefix	Covered	T1,T33,T4
MuxFuncPad	Covered	T1,T2,T16
MuxZeroEnd	Covered	T1,T2,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T16
MuxPrefix	Covered	T1,T33,T4
MuxFuncPad	Covered	T1,T2,T16
MuxZeroEnd	Covered	T1,T2,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T1,T2,T16
MuxPrefix	Covered	T1,T33,T4
MuxFuncPad	Covered	T1,T2,T16
MuxZeroEnd	Covered	T1,T2,T16
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T16
0	0	1	Covered	T1,T2,T16
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	680	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T1,T2,T3
7'b0000001	Covered	T1,T2,T16
7'b0000011	Covered	T1,T2,T16
7'b0000111	Covered	T1,T2,T16
7'b0001111	Covered	T1,T2,T16
7'b0011111	Covered	T1,T2,T16
7'b0111111	Covered	T1,T2,T16
7'b1111111	Covered	T1,T2,T16
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	345051	0	0
AlwaysPartialMsgBuf_M	2147483647	196953	0	0
CompleteBlockWhenProcess_A	2147483647	332944	0	0
DoneCondition_M	2147483647	345046	0	0
DonePulse_A	2147483647	345046	0	0
KeccakAddrInRange_A	2147483647	52945128	0	0
KeccakRunPulse_A	2147483647	3065744	0	0
MessageCondition_M	2147483647	48219848	0	0
ModeStableDuringOp_M	2147483647	34247	0	0
MsgReadyCondition_A	2147483647	2053952272	0	0
MsgWidthidth_A	1025	1025	0	0
NoPartialMsgFifo_M	2147483647	48022895	0	0
Pad01NotAttheEndOfBlock_A	2147483647	334367	0	0
PartialEndOfMsg_M	2147483647	196953	0	0
PrefixLessThanBlock_A	1025	1025	0	0
ProcessCondition_M	2147483647	345070	0	0
ProcessPulse_A	2147483647	345070	0	0
StartCondition_M	2147483647	345124	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	345124	0	0
StrengthStableDuringOp_M	2147483647	41280	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345051	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196953	0	0
T1	985024	151	0	0
T2	224130	340	0	0
T3	2357	0	0	0
T4	112135	0	0	0
T7	198548	134	0	0
T8	0	237	0	0
T9	0	87	0	0
T16	234675	1058	0	0
T33	14205	9	0	0
T34	722302	48	0	0
T35	654242	340	0	0
T36	1894	0	0	0
T37	0	45	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	332944	0	0
T1	985024	163	0	0
T2	224130	372	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	152	0	0
T8	0	251	0	0
T16	234675	2283	0	0
T33	14205	9	0	0
T34	722302	47	0	0
T35	654242	372	0	0
T36	1894	0	0	0
T37	0	56	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345046	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345046	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52945128	0	0
T1	985024	123560	0	0
T2	224130	99756	0	0
T3	2357	0	0	0
T4	112135	612	0	0
T7	198548	59172	0	0
T8	0	33381	0	0
T16	234675	276087	0	0
T33	14205	607	0	0
T34	722302	35466	0	0
T35	654242	99756	0	0
T36	1894	0	0	0
T37	0	43024	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3065744	0	0
T1	985024	6572	0	0
T2	224130	5542	0	0
T3	2357	0	0	0
T4	112135	36	0	0
T7	198548	3228	0	0
T8	0	1837	0	0
T16	234675	13147	0	0
T33	14205	31	0	0
T34	722302	1876	0	0
T35	654242	5542	0	0
T36	1894	0	0	0
T37	0	2276	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48219848	0	0
T1	985024	119139	0	0
T2	224130	96112	0	0
T3	2357	0	0	0
T4	112135	204	0	0
T7	198548	55219	0	0
T8	0	27227	0	0
T16	234675	241576	0	0
T33	14205	286	0	0
T34	722302	34155	0	0
T35	654242	96112	0	0
T36	1894	0	0	0
T37	0	41692	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34247	0	0
T1	985024	56	0	0
T2	224130	0	0	0
T3	2357	4	0	0
T4	112135	26	0	0
T7	198548	120	0	0
T8	0	201	0	0
T9	0	54	0	0
T16	234675	1	0	0
T33	14205	1	0	0
T34	722302	15	0	0
T35	654242	0	0	0
T36	1894	0	0	0
T37	0	27	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053952272	0	0
T1	985024	844556	0	0
T2	224130	126548	0	0
T3	2357	0	0	0
T4	112135	98711	0	0
T7	198548	109012	0	0
T8	0	183564	0	0
T16	234675	194653	0	0
T33	14205	957	0	0
T34	722302	354387	0	0
T35	654242	574812	0	0
T36	1894	0	0	0
T37	0	435803	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48022895	0	0
T1	985024	118988	0	0
T2	224130	95772	0	0
T3	2357	0	0	0
T4	112135	204	0	0
T7	198548	55085	0	0
T8	0	26990	0	0
T16	234675	240518	0	0
T33	14205	277	0	0
T34	722302	34107	0	0
T35	654242	95772	0	0
T36	1894	0	0	0
T37	0	41647	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	334367	0	0
T1	985024	165	0	0
T2	224130	374	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	155	0	0
T8	0	253	0	0
T16	234675	2289	0	0
T33	14205	9	0	0
T34	722302	47	0	0
T35	654242	374	0	0
T36	1894	0	0	0
T37	0	56	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196953	0	0
T1	985024	151	0	0
T2	224130	340	0	0
T3	2357	0	0	0
T4	112135	0	0	0
T7	198548	134	0	0
T8	0	237	0	0
T9	0	87	0	0
T16	234675	1058	0	0
T33	14205	9	0	0
T34	722302	48	0	0
T35	654242	340	0	0
T36	1894	0	0	0
T37	0	45	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345070	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345070	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345124	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	985024	985017	0	0
T2	224130	224122	0	0
T3	2357	2307	0	0
T4	112135	112054	0	0
T7	198548	198506	0	0
T16	234675	234675	0	0
T33	14205	14148	0	0
T34	722302	722219	0	0
T35	654242	654234	0	0
T36	1894	1834	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345124	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41280	0	0
T1	985024	95	0	0
T2	224130	2	0	0
T3	2357	4	0	0
T4	112135	22	0	0
T7	198548	122	0	0
T16	234675	1	0	0
T33	14205	2	0	0
T34	722302	30	0	0
T35	654242	2	0	0
T36	1894	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	985024	985017	0	0
T2	224130	224122	0	0
T3	2357	2307	0	0
T4	112135	112054	0	0
T7	198548	198506	0	0
T16	234675	234675	0	0
T33	14205	14148	0	0
T34	722302	722219	0	0
T35	654242	654234	0	0
T36	1894	1834	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	33503503	0
StMessageFeed_C	2147483647	2056979063	0
StPadSendMsg_C	2147483647	3844786	0
StPad_C	2147483647	334367	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	33503503	0
T1	985024	16781	0
T2	224130	37842	0
T3	2357	0	0
T4	112135	1164	0
T7	198548	15520	0
T8	0	26384	0
T16	234675	226689	0
T33	14205	873	0
T34	722302	5044	0
T35	654242	37857	0
T36	1894	0	0
T37	0	5529	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2056979063	0
T1	985024	845200	0
T2	224130	127102	0
T3	2357	0	0
T4	112135	98735	0
T7	198548	109323	0
T8	0	183729	0
T16	234675	194784	0
T33	14205	979	0
T34	722302	356219	0
T35	654242	575366	0
T36	1894	0	0
T37	0	438040	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3844786	0
T1	985024	1781	0
T2	224130	3594	0
T3	2357	0	0
T4	112135	192	0
T7	198548	1687	0
T8	0	2555	0
T16	234675	33232	0
T33	14205	144	0
T34	722302	471	0
T35	654242	3594	0
T36	1894	0	0
T37	0	565	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	334367	0
T1	985024	165	0
T2	224130	374	0
T3	2357	0	0
T4	112135	12	0
T7	198548	155	0
T8	0	253	0
T16	234675	2289	0
T33	14205	9	0
T34	722302	47	0
T35	654242	374	0
T36	1894	0	0
T37	0	56	0