Unified Coverage Report :: Module :: sha3pad_assert_if

Module : sha3pad_assert_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_cov_0/sha3pad_assert_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sha3pad_assert_cov_if	100.00						100.00

---

Module Instance : tb.dut.sha3pad_assert_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sha3pad_assert_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ProcessToRun_A	2147483647	345070	0	0
RunThenComplete_M	2147483647	3065699	0	0

ProcessToRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	345070	0	0
T1	985024	173	0	0
T2	224130	390	0	0
T3	2357	0	0	0
T4	112135	12	0	0
T7	198548	160	0	0
T8	0	272	0	0
T16	234675	2337	0	0
T33	14205	9	0	0
T34	722302	52	0	0
T35	654242	390	0	0
T36	1894	0	0	0
T37	0	57	0	0

RunThenComplete_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3065699	0	0
T1	985024	6572	0	0
T2	224130	5542	0	0
T3	2357	0	0	0
T4	112135	36	0	0
T7	198548	3228	0	0
T8	0	1837	0	0
T16	234675	13147	0	0
T33	14205	31	0	0
T34	722302	1876	0	0
T35	654242	5542	0	0
T36	1894	0	0	0
T37	0	2276	0	0