Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	949809	0	0
entropy_period_rd_A	2147483647	2826	0	0
intr_enable_rd_A	2147483647	3456	0	0
prefix_0_rd_A	2147483647	2577	0	0
prefix_10_rd_A	2147483647	2533	0	0
prefix_1_rd_A	2147483647	2500	0	0
prefix_2_rd_A	2147483647	2560	0	0
prefix_3_rd_A	2147483647	2597	0	0
prefix_4_rd_A	2147483647	2587	0	0
prefix_5_rd_A	2147483647	2562	0	0
prefix_6_rd_A	2147483647	2592	0	0
prefix_7_rd_A	2147483647	2510	0	0
prefix_8_rd_A	2147483647	2576	0	0
prefix_9_rd_A	2147483647	2574	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	949809	0	0
T5	161162	0	0	0
T6	160835	0	0	0
T9	588468	59137	0	0
T17	119592	0	0	0
T25	0	6129	0	0
T38	465378	0	0	0
T39	204246	0	0	0
T45	0	20636	0	0
T59	0	78259	0	0
T62	528053	0	0	0
T63	530221	0	0	0
T64	37998	0	0	0
T65	147811	0	0	0
T80	0	52449	0	0
T117	0	52591	0	0
T118	0	78969	0	0
T119	0	17183	0	0
T120	0	93992	0	0
T121	0	78733	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2826	0	0
T80	585078	174	0	0
T81	0	20	0	0
T110	0	59	0	0
T130	0	8	0	0
T131	0	9	0	0
T132	0	417	0	0
T133	0	6	0	0
T134	0	4	0	0
T135	0	22	0	0
T136	0	4	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3456	0	0
T80	585078	108	0	0
T81	0	20	0	0
T110	0	57	0	0
T114	0	14	0	0
T130	0	6	0	0
T131	0	18	0	0
T132	0	398	0	0
T133	0	8	0	0
T134	0	12	0	0
T135	0	34	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2577	0	0
T80	585078	114	0	0
T81	0	18	0	0
T110	0	48	0	0
T115	0	7	0	0
T130	0	4	0	0
T131	0	6	0	0
T132	0	437	0	0
T133	0	8	0	0
T134	0	9	0	0
T135	0	25	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2533	0	0
T80	585078	114	0	0
T81	0	17	0	0
T110	0	35	0	0
T115	0	3	0	0
T130	0	9	0	0
T131	0	7	0	0
T132	0	449	0	0
T133	0	6	0	0
T134	0	5	0	0
T135	0	10	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2500	0	0
T80	585078	188	0	0
T81	0	19	0	0
T110	0	57	0	0
T130	0	6	0	0
T132	0	373	0	0
T133	0	8	0	0
T134	0	1	0	0
T135	0	8	0	0
T136	0	3	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0
T146	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2560	0	0
T80	585078	137	0	0
T81	0	15	0	0
T110	0	36	0	0
T115	0	7	0	0
T131	0	17	0	0
T132	0	423	0	0
T133	0	8	0	0
T134	0	6	0	0
T135	0	6	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0
T146	0	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2597	0	0
T80	585078	144	0	0
T81	0	20	0	0
T110	0	47	0	0
T130	0	11	0	0
T131	0	6	0	0
T132	0	418	0	0
T133	0	5	0	0
T134	0	3	0	0
T135	0	12	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0
T146	0	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2587	0	0
T80	585078	131	0	0
T81	0	31	0	0
T110	0	44	0	0
T115	0	5	0	0
T130	0	4	0	0
T132	0	421	0	0
T133	0	9	0	0
T134	0	2	0	0
T135	0	16	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0
T146	0	6	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2562	0	0
T80	585078	158	0	0
T81	0	22	0	0
T110	0	46	0	0
T115	0	3	0	0
T130	0	8	0	0
T132	0	408	0	0
T133	0	3	0	0
T134	0	5	0	0
T135	0	15	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0
T146	0	9	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2592	0	0
T80	585078	64	0	0
T81	0	23	0	0
T110	0	51	0	0
T115	0	5	0	0
T130	0	2	0	0
T131	0	5	0	0
T132	0	359	0	0
T133	0	4	0	0
T134	0	6	0	0
T135	0	24	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2510	0	0
T80	585078	125	0	0
T81	0	13	0	0
T110	0	48	0	0
T115	0	2	0	0
T130	0	5	0	0
T131	0	10	0	0
T132	0	459	0	0
T133	0	10	0	0
T134	0	3	0	0
T135	0	18	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2576	0	0
T80	585078	88	0	0
T81	0	15	0	0
T110	0	41	0	0
T115	0	3	0	0
T130	0	9	0	0
T131	0	18	0	0
T132	0	423	0	0
T133	0	5	0	0
T134	0	7	0	0
T135	0	8	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T80	585078	170	0	0
T81	0	18	0	0
T110	0	50	0	0
T115	0	4	0	0
T130	0	8	0	0
T132	0	413	0	0
T133	0	7	0	0
T134	0	7	0	0
T135	0	22	0	0
T137	492527	0	0	0
T138	737176	0	0	0
T139	65813	0	0	0
T140	24092	0	0	0
T141	338320	0	0	0
T142	227308	0	0	0
T143	25561	0	0	0
T144	52072	0	0	0
T145	361426	0	0	0
T146	0	2	0	0