Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161442 |
1 |
|
|
T2 |
889 |
|
T3 |
261 |
|
T7 |
674 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
81194 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60938 |
1 |
|
|
T2 |
876 |
|
T3 |
5 |
|
T7 |
662 |
seven_bytes |
2800 |
1 |
|
|
T3 |
8 |
|
T18 |
19 |
|
T19 |
15 |
six_bytes |
2670 |
1 |
|
|
T3 |
7 |
|
T18 |
9 |
|
T19 |
6 |
five_bytes |
2795 |
1 |
|
|
T3 |
6 |
|
T18 |
7 |
|
T19 |
8 |
four_bytes |
2819 |
1 |
|
|
T3 |
5 |
|
T18 |
13 |
|
T19 |
7 |
three_bytes |
2743 |
1 |
|
|
T3 |
10 |
|
T18 |
6 |
|
T19 |
12 |
two_bytes |
2715 |
1 |
|
|
T3 |
5 |
|
T18 |
13 |
|
T19 |
8 |
one_byte |
2768 |
1 |
|
|
T3 |
5 |
|
T18 |
8 |
|
T19 |
8 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
158252 |
1 |
|
|
T2 |
863 |
|
T3 |
259 |
|
T7 |
650 |
auto[1] |
3190 |
1 |
|
|
T2 |
26 |
|
T3 |
2 |
|
T7 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161442 |
1 |
|
|
T2 |
889 |
|
T3 |
261 |
|
T7 |
674 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
161421 |
1 |
|
|
T2 |
889 |
|
T3 |
261 |
|
T7 |
674 |
auto[1] |
21 |
1 |
|
|
T185 |
1 |
|
T186 |
1 |
|
T86 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1128 |
1 |
|
|
T2 |
13 |
|
T7 |
12 |
|
T20 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3190 |
1 |
|
|
T2 |
26 |
|
T3 |
2 |
|
T7 |
24 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165488 |
1 |
|
|
T2 |
414 |
|
T3 |
985 |
|
T7 |
627 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
83191 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62781 |
1 |
|
|
T2 |
407 |
|
T3 |
24 |
|
T7 |
613 |
seven_bytes |
2764 |
1 |
|
|
T3 |
20 |
|
T18 |
3 |
|
T19 |
9 |
six_bytes |
2732 |
1 |
|
|
T3 |
30 |
|
T18 |
2 |
|
T19 |
10 |
five_bytes |
2841 |
1 |
|
|
T3 |
35 |
|
T18 |
5 |
|
T19 |
3 |
four_bytes |
2774 |
1 |
|
|
T3 |
28 |
|
T18 |
3 |
|
T19 |
10 |
three_bytes |
2838 |
1 |
|
|
T3 |
29 |
|
T18 |
4 |
|
T19 |
9 |
two_bytes |
2710 |
1 |
|
|
T3 |
38 |
|
T18 |
2 |
|
T19 |
7 |
one_byte |
2857 |
1 |
|
|
T3 |
26 |
|
T18 |
2 |
|
T19 |
10 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
162262 |
1 |
|
|
T2 |
400 |
|
T3 |
973 |
|
T7 |
599 |
auto[1] |
3226 |
1 |
|
|
T2 |
14 |
|
T3 |
12 |
|
T7 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165488 |
1 |
|
|
T2 |
414 |
|
T3 |
985 |
|
T7 |
627 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165478 |
1 |
|
|
T2 |
414 |
|
T3 |
985 |
|
T7 |
626 |
auto[1] |
10 |
1 |
|
|
T7 |
1 |
|
T187 |
1 |
|
T188 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1156 |
1 |
|
|
T2 |
7 |
|
T3 |
2 |
|
T7 |
14 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3226 |
1 |
|
|
T2 |
14 |
|
T3 |
12 |
|
T7 |
28 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
322806 |
1 |
|
|
T2 |
1631 |
|
T3 |
270 |
|
T7 |
2504 |
auto[1] |
423 |
1 |
|
|
T8 |
20 |
|
T9 |
26 |
|
T10 |
80 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
166737 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
116910 |
1 |
|
|
T2 |
1608 |
|
T3 |
5 |
|
T7 |
2472 |
seven_bytes |
5694 |
1 |
|
|
T3 |
13 |
|
T18 |
15 |
|
T19 |
58 |
six_bytes |
5694 |
1 |
|
|
T3 |
5 |
|
T18 |
13 |
|
T19 |
47 |
five_bytes |
5723 |
1 |
|
|
T3 |
10 |
|
T18 |
24 |
|
T19 |
52 |
four_bytes |
5609 |
1 |
|
|
T3 |
7 |
|
T18 |
15 |
|
T19 |
55 |
three_bytes |
5610 |
1 |
|
|
T3 |
6 |
|
T18 |
10 |
|
T19 |
40 |
two_bytes |
5664 |
1 |
|
|
T3 |
8 |
|
T18 |
12 |
|
T19 |
43 |
one_byte |
5588 |
1 |
|
|
T3 |
6 |
|
T18 |
15 |
|
T19 |
38 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
317059 |
1 |
|
|
T2 |
1585 |
|
T3 |
264 |
|
T7 |
2440 |
auto[1] |
6170 |
1 |
|
|
T2 |
46 |
|
T3 |
6 |
|
T7 |
64 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323229 |
1 |
|
|
T2 |
1631 |
|
T3 |
270 |
|
T7 |
2504 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323205 |
1 |
|
|
T2 |
1631 |
|
T3 |
270 |
|
T7 |
2504 |
auto[1] |
24 |
1 |
|
|
T64 |
1 |
|
T187 |
1 |
|
T66 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2107 |
1 |
|
|
T2 |
23 |
|
T7 |
32 |
|
T20 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6170 |
1 |
|
|
T2 |
46 |
|
T3 |
6 |
|
T7 |
64 |