Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258825651

1

T1

118542

T2

33446

T3

8533

full_word

182106785

1

T1

793162

T2

40620

T3

12484

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	440932166	1			T1	197858		T2	74066		T3	21017
auto[TlIntgErrCmd]	77	1			T136	6		T137	2		T138	4
auto[TlIntgErrData]	95	1			T136	1		T137	8		T138	4
auto[TlIntgErrBoth]	98	1			T136	3		T137	10		T138	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227225524

1

T1

104137

T2

52865

T3

13584

auto[1]

213706912

1

T1

937207

T2

21201

T3

7433

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156816605	1			T1	716208		T2	24536		T3	5387
auto[TlIntgErrNone]	partial	auto[1]	102008800	1			T1	469214		T2	8910		T3	3146
auto[TlIntgErrNone]	full_word	auto[0]	70408781	1			T1	325169		T2	28329		T3	8197
auto[TlIntgErrNone]	full_word	auto[1]	111697980	1			T1	467993		T2	12291		T3	4287
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T136	2		T138	2		T194	1
auto[TlIntgErrCmd]	partial	auto[1]	35	1			T136	3		T137	1		T138	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T136	1		T137	1		T194	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T191	1		T195	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T137	2		T138	2		T194	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T136	1		T137	3		T138	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T137	1		T196	1		T197	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T137	2		T190	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T137	5		T138	1		T194	3
auto[TlIntgErrBoth]	partial	auto[1]	38	1			T136	3		T137	2		T138	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T137	2		T198	1		T193	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T137	1		T197	1		T192	1