Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	560257	0	0
entropy_period_rd_A	2147483647	1299	0	0
intr_enable_rd_A	2147483647	2080	0	0
prefix_0_rd_A	2147483647	1389	0	0
prefix_10_rd_A	2147483647	1502	0	0
prefix_1_rd_A	2147483647	1523	0	0
prefix_2_rd_A	2147483647	1385	0	0
prefix_3_rd_A	2147483647	1420	0	0
prefix_4_rd_A	2147483647	1395	0	0
prefix_5_rd_A	2147483647	1386	0	0
prefix_6_rd_A	2147483647	1303	0	0
prefix_7_rd_A	2147483647	1482	0	0
prefix_8_rd_A	2147483647	1480	0	0
prefix_9_rd_A	2147483647	1433	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	560257	0	0
T15	310064	27779	0	0
T24	0	5669	0	0
T25	0	7491	0	0
T55	0	60496	0	0
T56	0	31505	0	0
T64	122261	0	0	0
T81	0	62148	0	0
T117	112609	0	0	0
T143	0	39176	0	0
T144	0	53519	0	0
T145	0	71557	0	0
T146	0	8675	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1299	0	0
T15	310064	38	0	0
T25	0	3	0	0
T64	122261	0	0	0
T81	0	140	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	1	0	0
T169	0	34	0	0
T170	0	3	0	0
T171	0	79	0	0
T172	0	9	0	0
T173	0	3	0	0
T174	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2080	0	0
T15	310064	52	0	0
T25	0	28	0	0
T64	122261	0	0	0
T81	0	201	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	8	0	0
T169	0	20	0	0
T170	0	11	0	0
T171	0	133	0	0
T175	0	8	0	0
T176	0	28	0	0
T177	0	6	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1389	0	0
T15	310064	32	0	0
T25	0	14	0	0
T64	122261	0	0	0
T81	0	86	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	3	0	0
T169	0	23	0	0
T170	0	5	0	0
T171	0	159	0	0
T172	0	3	0	0
T174	0	12	0	0
T178	0	237	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1502	0	0
T15	310064	28	0	0
T25	0	23	0	0
T64	122261	0	0	0
T81	0	147	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T169	0	63	0	0
T170	0	6	0	0
T171	0	139	0	0
T172	0	22	0	0
T174	0	7	0	0
T175	0	4	0	0
T178	0	262	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T15	310064	60	0	0
T25	0	12	0	0
T64	122261	0	0	0
T81	0	150	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	8	0	0
T169	0	38	0	0
T170	0	2	0	0
T171	0	177	0	0
T172	0	3	0	0
T174	0	13	0	0
T178	0	263	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1385	0	0
T15	310064	23	0	0
T25	0	4	0	0
T64	122261	0	0	0
T81	0	164	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T169	0	21	0	0
T170	0	6	0	0
T171	0	107	0	0
T172	0	5	0	0
T173	0	6	0	0
T175	0	2	0	0
T177	0	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1420	0	0
T15	310064	91	0	0
T25	0	31	0	0
T64	122261	0	0	0
T81	0	169	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	4	0	0
T169	0	35	0	0
T170	0	2	0	0
T171	0	115	0	0
T174	0	10	0	0
T175	0	6	0	0
T178	0	209	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1395	0	0
T15	310064	45	0	0
T25	0	15	0	0
T64	122261	0	0	0
T81	0	149	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	4	0	0
T169	0	42	0	0
T170	0	6	0	0
T171	0	106	0	0
T172	0	3	0	0
T175	0	4	0	0
T177	0	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1386	0	0
T15	310064	31	0	0
T25	0	7	0	0
T64	122261	0	0	0
T81	0	129	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T169	0	28	0	0
T170	0	14	0	0
T171	0	144	0	0
T172	0	12	0	0
T174	0	10	0	0
T175	0	9	0	0
T177	0	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T15	310064	58	0	0
T25	0	11	0	0
T64	122261	0	0	0
T81	0	98	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T169	0	39	0	0
T170	0	8	0	0
T171	0	128	0	0
T172	0	6	0	0
T174	0	10	0	0
T175	0	1	0	0
T178	0	177	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T15	310064	35	0	0
T25	0	26	0	0
T64	122261	0	0	0
T81	0	156	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	3	0	0
T169	0	65	0	0
T170	0	13	0	0
T171	0	99	0	0
T172	0	8	0	0
T178	0	227	0	0
T179	0	10	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1480	0	0
T15	310064	28	0	0
T25	0	24	0	0
T64	122261	0	0	0
T81	0	123	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T169	0	46	0	0
T170	0	3	0	0
T171	0	139	0	0
T172	0	8	0	0
T173	0	3	0	0
T175	0	2	0	0
T177	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1433	0	0
T15	310064	36	0	0
T25	0	31	0	0
T64	122261	0	0	0
T81	0	175	0	0
T117	112609	0	0	0
T147	270761	0	0	0
T148	131361	0	0	0
T149	39066	0	0	0
T150	19404	0	0	0
T151	152553	0	0	0
T152	646746	0	0	0
T153	965977	0	0	0
T168	0	5	0	0
T169	0	37	0	0
T170	0	10	0	0
T171	0	144	0	0
T172	0	2	0	0
T173	0	8	0	0
T175	0	7	0	0