Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172651 |
1 |
|
|
T3 |
940 |
|
T6 |
238 |
|
T7 |
2194 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91043 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59748 |
1 |
|
|
T3 |
26 |
|
T6 |
236 |
|
T7 |
54 |
seven_bytes |
3149 |
1 |
|
|
T3 |
25 |
|
T7 |
57 |
|
T20 |
54 |
six_bytes |
3118 |
1 |
|
|
T3 |
27 |
|
T7 |
77 |
|
T20 |
45 |
five_bytes |
3066 |
1 |
|
|
T3 |
20 |
|
T7 |
56 |
|
T20 |
49 |
four_bytes |
3113 |
1 |
|
|
T3 |
31 |
|
T7 |
57 |
|
T20 |
46 |
three_bytes |
3165 |
1 |
|
|
T3 |
20 |
|
T7 |
69 |
|
T20 |
51 |
two_bytes |
3156 |
1 |
|
|
T3 |
19 |
|
T7 |
74 |
|
T20 |
55 |
one_byte |
3093 |
1 |
|
|
T3 |
28 |
|
T7 |
63 |
|
T20 |
55 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169355 |
1 |
|
|
T3 |
930 |
|
T6 |
234 |
|
T7 |
2168 |
auto[1] |
3296 |
1 |
|
|
T3 |
10 |
|
T6 |
4 |
|
T7 |
26 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172651 |
1 |
|
|
T3 |
940 |
|
T6 |
238 |
|
T7 |
2194 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172642 |
1 |
|
|
T3 |
940 |
|
T6 |
238 |
|
T7 |
2194 |
auto[1] |
9 |
1 |
|
|
T183 |
1 |
|
T184 |
1 |
|
T185 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1157 |
1 |
|
|
T6 |
2 |
|
T7 |
8 |
|
T20 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3296 |
1 |
|
|
T3 |
10 |
|
T6 |
4 |
|
T7 |
26 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176055 |
1 |
|
|
T3 |
1721 |
|
T6 |
335 |
|
T7 |
1531 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
94111 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
59544 |
1 |
|
|
T3 |
41 |
|
T6 |
82 |
|
T7 |
49 |
seven_bytes |
3210 |
1 |
|
|
T3 |
57 |
|
T6 |
6 |
|
T7 |
47 |
six_bytes |
3244 |
1 |
|
|
T3 |
42 |
|
T6 |
7 |
|
T7 |
41 |
five_bytes |
3212 |
1 |
|
|
T3 |
38 |
|
T6 |
9 |
|
T7 |
48 |
four_bytes |
3227 |
1 |
|
|
T3 |
42 |
|
T6 |
7 |
|
T7 |
48 |
three_bytes |
3121 |
1 |
|
|
T3 |
39 |
|
T6 |
8 |
|
T7 |
21 |
two_bytes |
3213 |
1 |
|
|
T3 |
36 |
|
T6 |
8 |
|
T7 |
34 |
one_byte |
3173 |
1 |
|
|
T3 |
59 |
|
T6 |
6 |
|
T7 |
41 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172703 |
1 |
|
|
T3 |
1703 |
|
T6 |
331 |
|
T7 |
1507 |
auto[1] |
3352 |
1 |
|
|
T3 |
18 |
|
T6 |
4 |
|
T7 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176055 |
1 |
|
|
T3 |
1721 |
|
T6 |
335 |
|
T7 |
1531 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176037 |
1 |
|
|
T3 |
1721 |
|
T6 |
335 |
|
T7 |
1531 |
auto[1] |
18 |
1 |
|
|
T17 |
2 |
|
T103 |
1 |
|
T71 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1151 |
1 |
|
|
T3 |
3 |
|
T6 |
2 |
|
T7 |
9 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3352 |
1 |
|
|
T3 |
18 |
|
T6 |
4 |
|
T7 |
24 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329389 |
1 |
|
|
T3 |
932 |
|
T6 |
986 |
|
T7 |
1044 |
auto[1] |
523 |
1 |
|
|
T8 |
29 |
|
T9 |
99 |
|
T10 |
106 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
170217 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
119587 |
1 |
|
|
T3 |
23 |
|
T6 |
458 |
|
T7 |
110 |
seven_bytes |
5745 |
1 |
|
|
T3 |
24 |
|
T6 |
10 |
|
T7 |
23 |
six_bytes |
5854 |
1 |
|
|
T3 |
25 |
|
T6 |
13 |
|
T7 |
38 |
five_bytes |
5712 |
1 |
|
|
T3 |
21 |
|
T6 |
20 |
|
T7 |
27 |
four_bytes |
5753 |
1 |
|
|
T3 |
21 |
|
T6 |
13 |
|
T7 |
22 |
three_bytes |
5707 |
1 |
|
|
T3 |
23 |
|
T6 |
19 |
|
T7 |
24 |
two_bytes |
5639 |
1 |
|
|
T3 |
29 |
|
T6 |
12 |
|
T7 |
18 |
one_byte |
5698 |
1 |
|
|
T3 |
22 |
|
T6 |
22 |
|
T7 |
20 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323448 |
1 |
|
|
T3 |
916 |
|
T6 |
966 |
|
T7 |
1026 |
auto[1] |
6464 |
1 |
|
|
T3 |
16 |
|
T6 |
20 |
|
T7 |
18 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329912 |
1 |
|
|
T3 |
932 |
|
T6 |
986 |
|
T7 |
1044 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329889 |
1 |
|
|
T3 |
932 |
|
T6 |
986 |
|
T7 |
1044 |
auto[1] |
23 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T186 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2230 |
1 |
|
|
T3 |
4 |
|
T6 |
7 |
|
T7 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6464 |
1 |
|
|
T3 |
16 |
|
T6 |
20 |
|
T7 |
18 |