Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265890818

1

T1

563746

T2

145

T3

40229

full_word

186308561

1

T1

344546

T2

342

T3

58393

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	452199089	1			T1	908292		T2	487		T3	98622
auto[TlIntgErrCmd]	97	1			T131	9		T132	5		T133	6
auto[TlIntgErrData]	95	1			T131	7		T133	8		T195	3
auto[TlIntgErrBoth]	98	1			T131	4		T132	5		T133	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234194807

1

T1

454025

T2

133

T3

66104

auto[1]

218004572

1

T1

454267

T2

354

T3

32518

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161739203	1			T1	336483		T2	123		T3	25859
auto[TlIntgErrNone]	partial	auto[1]	104151348	1			T1	227263		T2	22		T3	14370
auto[TlIntgErrNone]	full_word	auto[0]	72455478	1			T1	117542		T2	10		T3	40245
auto[TlIntgErrNone]	full_word	auto[1]	113853060	1			T1	227004		T2	332		T3	18148
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T131	4		T132	2		T133	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T131	4		T132	3		T133	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T193	1		T190	1		T191	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T131	1		T188	1		T194	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T131	2		T133	3		T188	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T131	4		T133	5		T195	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T131	1		T189	1		T190	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T188	2		T191	2		T196	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T131	2		T132	2		T133	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T131	2		T132	3		T133	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T197	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T195	2		T192	1		T197	1