Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
7242 |
0 |
0 |
T4 |
138459 |
6 |
0 |
0 |
T5 |
0 |
6 |
0 |
0 |
T6 |
190873 |
6 |
0 |
0 |
T7 |
453202 |
18 |
0 |
0 |
T17 |
0 |
6 |
0 |
0 |
T33 |
483286 |
0 |
0 |
0 |
T34 |
18333 |
6 |
0 |
0 |
T35 |
1238 |
0 |
0 |
0 |
T36 |
2959 |
0 |
0 |
0 |
T37 |
618539 |
0 |
0 |
0 |
T38 |
185067 |
6 |
0 |
0 |
T42 |
0 |
6 |
0 |
0 |
T48 |
326157 |
6 |
0 |
0 |
T67 |
0 |
6 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
7242 |
0 |
0 |
T4 |
138459 |
6 |
0 |
0 |
T5 |
0 |
6 |
0 |
0 |
T6 |
190873 |
6 |
0 |
0 |
T7 |
453202 |
18 |
0 |
0 |
T17 |
0 |
6 |
0 |
0 |
T33 |
483286 |
0 |
0 |
0 |
T34 |
18333 |
6 |
0 |
0 |
T35 |
1238 |
0 |
0 |
0 |
T36 |
2959 |
0 |
0 |
0 |
T37 |
618539 |
0 |
0 |
0 |
T38 |
185067 |
6 |
0 |
0 |
T42 |
0 |
6 |
0 |
0 |
T48 |
326157 |
6 |
0 |
0 |
T67 |
0 |
6 |
0 |
0 |