Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	662920	0	0
entropy_period_rd_A	2147483647	1449	0	0
intr_enable_rd_A	2147483647	2003	0	0
prefix_0_rd_A	2147483647	1563	0	0
prefix_10_rd_A	2147483647	1522	0	0
prefix_1_rd_A	2147483647	1530	0	0
prefix_2_rd_A	2147483647	1547	0	0
prefix_3_rd_A	2147483647	1487	0	0
prefix_4_rd_A	2147483647	1519	0	0
prefix_5_rd_A	2147483647	1562	0	0
prefix_6_rd_A	2147483647	1443	0	0
prefix_7_rd_A	2147483647	1562	0	0
prefix_8_rd_A	2147483647	1547	0	0
prefix_9_rd_A	2147483647	1591	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	662920	0	0
T5	97578	0	0	0
T6	190873	28105	0	0
T7	453202	0	0	0
T34	18333	0	0	0
T37	618539	0	0	0
T38	185067	0	0	0
T39	0	59428	0	0
T42	495413	0	0	0
T43	611188	0	0	0
T47	0	44257	0	0
T48	326157	0	0	0
T62	0	36943	0	0
T63	0	156256	0	0
T64	0	36052	0	0
T66	1154	0	0	0
T86	0	34158	0	0
T138	0	18996	0	0
T139	0	18100	0	0
T140	0	69308	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T86	391602	111	0	0
T87	0	76	0	0
T156	0	3	0	0
T157	0	74	0	0
T158	0	7	0	0
T159	0	3	0	0
T160	0	34	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	12	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2003	0	0
T86	391602	52	0	0
T87	0	48	0	0
T156	0	2	0	0
T157	0	135	0	0
T158	0	7	0	0
T159	0	8	0	0
T160	0	30	0	0
T161	0	35	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T173	0	25	0	0
T174	0	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1563	0	0
T86	391602	114	0	0
T87	0	90	0	0
T156	0	12	0	0
T157	0	120	0	0
T158	0	1	0	0
T159	0	10	0	0
T160	0	12	0	0
T161	0	41	0	0
T162	0	2	0	0
T163	0	6	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1522	0	0
T86	391602	84	0	0
T87	0	66	0	0
T156	0	10	0	0
T157	0	138	0	0
T158	0	4	0	0
T159	0	4	0	0
T160	0	20	0	0
T161	0	28	0	0
T162	0	9	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T86	391602	129	0	0
T87	0	78	0	0
T156	0	3	0	0
T157	0	103	0	0
T158	0	3	0	0
T160	0	17	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	5	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T86	391602	94	0	0
T87	0	85	0	0
T156	0	8	0	0
T157	0	139	0	0
T158	0	5	0	0
T159	0	6	0	0
T160	0	23	0	0
T161	0	8	0	0
T162	0	2	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1487	0	0
T86	391602	115	0	0
T87	0	53	0	0
T156	0	6	0	0
T157	0	134	0	0
T158	0	6	0	0
T159	0	9	0	0
T160	0	17	0	0
T161	0	8	0	0
T162	0	7	0	0
T163	0	3	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1519	0	0
T86	391602	73	0	0
T87	0	60	0	0
T157	0	167	0	0
T158	0	7	0	0
T159	0	3	0	0
T160	0	15	0	0
T161	0	16	0	0
T162	0	4	0	0
T163	0	13	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T176	0	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1562	0	0
T86	391602	96	0	0
T87	0	53	0	0
T156	0	2	0	0
T157	0	143	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	16	0	0
T161	0	36	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	4	0	0
T177	0	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1443	0	0
T86	391602	81	0	0
T87	0	63	0	0
T156	0	3	0	0
T157	0	158	0	0
T158	0	5	0	0
T159	0	9	0	0
T160	0	15	0	0
T161	0	9	0	0
T162	0	4	0	0
T163	0	12	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1562	0	0
T86	391602	105	0	0
T87	0	125	0	0
T156	0	1	0	0
T157	0	122	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	10	0	0
T161	0	29	0	0
T162	0	1	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1547	0	0
T86	391602	129	0	0
T87	0	41	0	0
T156	0	4	0	0
T157	0	119	0	0
T158	0	7	0	0
T159	0	5	0	0
T160	0	9	0	0
T161	0	15	0	0
T162	0	3	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T86	391602	113	0	0
T87	0	68	0	0
T156	0	11	0	0
T157	0	145	0	0
T158	0	2	0	0
T160	0	16	0	0
T161	0	7	0	0
T162	0	5	0	0
T163	0	9	0	0
T164	905871	0	0	0
T165	476123	0	0	0
T166	195744	0	0	0
T167	526051	0	0	0
T168	2667	0	0	0
T169	10313	0	0	0
T170	901820	0	0	0
T171	3072	0	0	0
T172	869448	0	0	0
T175	0	6	0	0