Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260429551

1

T1

61335

T2

55774

T3

3993

full_word

183665907

1

T1

82989

T2

61654

T3

5990

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444095188	1			T1	144324		T2	117428		T3	9983
auto[TlIntgErrCmd]	82	1			T126	4		T127	1		T128	9
auto[TlIntgErrData]	94	1			T126	2		T127	3		T128	6
auto[TlIntgErrBoth]	94	1			T126	4		T127	6		T128	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228992355

1

T1

94521

T2

83779

T3

6709

auto[1]

215103103

1

T1

49803

T2

33649

T3

3274

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157751919	1			T1	38070		T2	40421		T3	2486
auto[TlIntgErrNone]	partial	auto[1]	102677383	1			T1	23265		T2	15353		T3	1507
auto[TlIntgErrNone]	full_word	auto[0]	71240330	1			T1	56451		T2	43358		T3	4223
auto[TlIntgErrNone]	full_word	auto[1]	112425556	1			T1	26538		T2	18296		T3	1767
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T126	1		T128	5		T176	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T126	3		T128	4		T158	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T127	1		T174	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T177	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T126	2		T127	1		T128	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T127	2		T128	2		T173	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T177	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T173	3		T178	1		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T126	1		T127	1		T128	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T126	2		T127	3		T128	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T127	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T126	1		T127	1		T176	4