Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	770863	0	0
entropy_period_rd_A	2147483647	1482	0	0
intr_enable_rd_A	2147483647	2485	0	0
prefix_0_rd_A	2147483647	1485	0	0
prefix_10_rd_A	2147483647	1659	0	0
prefix_1_rd_A	2147483647	1549	0	0
prefix_2_rd_A	2147483647	1554	0	0
prefix_3_rd_A	2147483647	1670	0	0
prefix_4_rd_A	2147483647	1597	0	0
prefix_5_rd_A	2147483647	1512	0	0
prefix_6_rd_A	2147483647	1555	0	0
prefix_7_rd_A	2147483647	1560	0	0
prefix_8_rd_A	2147483647	1490	0	0
prefix_9_rd_A	2147483647	1480	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	770863	0	0
T4	138981	0	0	0
T12	5372	0	0	0
T16	617122	93987	0	0
T19	869998	0	0	0
T36	103628	0	0	0
T37	10257	0	0	0
T38	523516	0	0	0
T49	107523	0	0	0
T50	21677	0	0	0
T55	0	20090	0	0
T58	0	99333	0	0
T118	501491	0	0	0
T132	0	63950	0	0
T133	0	133708	0	0
T134	0	32550	0	0
T135	0	66335	0	0
T136	0	67642	0	0
T137	0	27953	0	0
T138	0	87534	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1482	0	0
T89	3993	15	0	0
T96	6213	21	0	0
T126	10997	40	0	0
T149	1931	8	0	0
T150	8672	17	0	0
T151	5539	20	0	0
T152	2766	3	0	0
T153	4458	7	0	0
T154	8132	14	0	0
T155	2081	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2485	0	0
T126	10997	46	0	0
T129	1029	10	0	0
T131	1044	5	0	0
T149	1931	2	0	0
T150	8672	29	0	0
T151	5539	9	0	0
T152	2766	13	0	0
T153	4458	11	0	0
T154	8132	34	0	0
T156	1268	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1485	0	0
T89	3993	17	0	0
T96	6213	21	0	0
T126	10997	18	0	0
T150	8672	13	0	0
T151	5539	18	0	0
T153	4458	8	0	0
T154	8132	19	0	0
T155	2081	2	0	0
T157	1917	2	0	0
T158	11659	36	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1659	0	0
T89	3993	16	0	0
T96	6213	26	0	0
T126	10997	34	0	0
T149	1931	1	0	0
T150	8672	10	0	0
T151	5539	45	0	0
T152	2766	1	0	0
T153	4458	12	0	0
T154	8132	26	0	0
T155	2081	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1549	0	0
T89	3993	8	0	0
T96	6213	23	0	0
T126	10997	18	0	0
T150	8672	16	0	0
T151	5539	22	0	0
T152	2766	2	0	0
T153	4458	15	0	0
T154	8132	16	0	0
T155	2081	4	0	0
T157	1917	10	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1554	0	0
T89	3993	20	0	0
T96	6213	28	0	0
T126	10997	38	0	0
T149	1931	7	0	0
T150	8672	4	0	0
T151	5539	6	0	0
T153	4458	8	0	0
T154	8132	18	0	0
T158	11659	36	0	0
T159	2162	6	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1670	0	0
T89	3993	10	0	0
T96	6213	26	0	0
T126	10997	20	0	0
T149	1931	6	0	0
T150	8672	21	0	0
T151	5539	27	0	0
T153	4458	11	0	0
T154	8132	14	0	0
T155	2081	9	0	0
T157	1917	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1597	0	0
T89	3993	17	0	0
T96	6213	21	0	0
T126	10997	10	0	0
T149	1931	3	0	0
T150	8672	22	0	0
T151	5539	31	0	0
T152	2766	5	0	0
T153	4458	12	0	0
T154	8132	11	0	0
T155	2081	4	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1512	0	0
T89	3993	10	0	0
T96	6213	23	0	0
T126	10997	27	0	0
T149	1931	4	0	0
T150	8672	19	0	0
T151	5539	28	0	0
T152	2766	10	0	0
T153	4458	10	0	0
T154	8132	14	0	0
T155	2081	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1555	0	0
T89	3993	14	0	0
T96	6213	21	0	0
T126	10997	16	0	0
T150	8672	19	0	0
T151	5539	39	0	0
T152	2766	3	0	0
T153	4458	6	0	0
T154	8132	19	0	0
T155	2081	4	0	0
T157	1917	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1560	0	0
T89	3993	15	0	0
T96	6213	25	0	0
T126	10997	41	0	0
T149	1931	2	0	0
T150	8672	18	0	0
T151	5539	30	0	0
T153	4458	8	0	0
T154	8132	12	0	0
T157	1917	3	0	0
T158	11659	47	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1490	0	0
T89	3993	5	0	0
T96	6213	33	0	0
T126	10997	6	0	0
T149	1931	2	0	0
T150	8672	20	0	0
T151	5539	15	0	0
T152	2766	8	0	0
T153	4458	9	0	0
T154	8132	10	0	0
T155	2081	5	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1480	0	0
T89	3993	12	0	0
T96	6213	30	0	0
T126	10997	11	0	0
T149	1931	3	0	0
T150	8672	17	0	0
T151	5539	23	0	0
T152	2766	7	0	0
T153	4458	8	0	0
T154	8132	19	0	0
T155	2081	3	0	0