Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171612 |
1 |
|
|
T3 |
1782 |
|
T7 |
540 |
|
T8 |
550 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
85892 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65374 |
1 |
|
|
T3 |
53 |
|
T7 |
531 |
|
T8 |
17 |
seven_bytes |
2883 |
1 |
|
|
T3 |
48 |
|
T8 |
16 |
|
T38 |
3 |
six_bytes |
2920 |
1 |
|
|
T3 |
46 |
|
T8 |
18 |
|
T38 |
2 |
five_bytes |
3023 |
1 |
|
|
T3 |
39 |
|
T8 |
14 |
|
T38 |
6 |
four_bytes |
2836 |
1 |
|
|
T3 |
48 |
|
T8 |
8 |
|
T38 |
3 |
three_bytes |
2943 |
1 |
|
|
T3 |
39 |
|
T8 |
13 |
|
T38 |
4 |
two_bytes |
2871 |
1 |
|
|
T3 |
55 |
|
T8 |
13 |
|
T38 |
2 |
one_byte |
2870 |
1 |
|
|
T3 |
43 |
|
T8 |
11 |
|
T38 |
4 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168172 |
1 |
|
|
T3 |
1754 |
|
T7 |
522 |
|
T8 |
544 |
auto[1] |
3440 |
1 |
|
|
T3 |
28 |
|
T7 |
18 |
|
T8 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171612 |
1 |
|
|
T3 |
1782 |
|
T7 |
540 |
|
T8 |
550 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171596 |
1 |
|
|
T3 |
1782 |
|
T7 |
540 |
|
T8 |
550 |
auto[1] |
16 |
1 |
|
|
T5 |
1 |
|
T164 |
1 |
|
T165 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1217 |
1 |
|
|
T3 |
6 |
|
T7 |
9 |
|
T8 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3440 |
1 |
|
|
T3 |
28 |
|
T7 |
18 |
|
T8 |
6 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176319 |
1 |
|
|
T3 |
1445 |
|
T7 |
451 |
|
T8 |
204 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
89410 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65552 |
1 |
|
|
T3 |
39 |
|
T7 |
445 |
|
T8 |
5 |
seven_bytes |
3079 |
1 |
|
|
T3 |
32 |
|
T8 |
5 |
|
T38 |
18 |
six_bytes |
3033 |
1 |
|
|
T3 |
37 |
|
T8 |
9 |
|
T38 |
12 |
five_bytes |
3081 |
1 |
|
|
T3 |
46 |
|
T8 |
9 |
|
T38 |
18 |
four_bytes |
3056 |
1 |
|
|
T3 |
47 |
|
T8 |
3 |
|
T38 |
9 |
three_bytes |
3044 |
1 |
|
|
T3 |
45 |
|
T8 |
6 |
|
T38 |
13 |
two_bytes |
3061 |
1 |
|
|
T3 |
32 |
|
T8 |
6 |
|
T38 |
15 |
one_byte |
3003 |
1 |
|
|
T3 |
49 |
|
T8 |
4 |
|
T38 |
16 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172917 |
1 |
|
|
T3 |
1425 |
|
T7 |
439 |
|
T8 |
200 |
auto[1] |
3402 |
1 |
|
|
T3 |
20 |
|
T7 |
12 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176319 |
1 |
|
|
T3 |
1445 |
|
T7 |
451 |
|
T8 |
204 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
176306 |
1 |
|
|
T3 |
1445 |
|
T7 |
451 |
|
T8 |
204 |
auto[1] |
13 |
1 |
|
|
T166 |
1 |
|
T9 |
1 |
|
T167 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1208 |
1 |
|
|
T3 |
6 |
|
T7 |
6 |
|
T37 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3402 |
1 |
|
|
T3 |
20 |
|
T7 |
12 |
|
T8 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
331737 |
1 |
|
|
T3 |
2883 |
|
T7 |
623 |
|
T8 |
1100 |
auto[1] |
753 |
1 |
|
|
T5 |
105 |
|
T9 |
99 |
|
T10 |
67 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
163409 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
130421 |
1 |
|
|
T3 |
159 |
|
T7 |
611 |
|
T8 |
25 |
seven_bytes |
5457 |
1 |
|
|
T3 |
73 |
|
T8 |
28 |
|
T38 |
79 |
six_bytes |
5531 |
1 |
|
|
T3 |
89 |
|
T8 |
29 |
|
T38 |
68 |
five_bytes |
5554 |
1 |
|
|
T3 |
76 |
|
T8 |
33 |
|
T38 |
68 |
four_bytes |
5542 |
1 |
|
|
T3 |
86 |
|
T8 |
32 |
|
T38 |
73 |
three_bytes |
5529 |
1 |
|
|
T3 |
69 |
|
T8 |
34 |
|
T38 |
48 |
two_bytes |
5617 |
1 |
|
|
T3 |
67 |
|
T8 |
33 |
|
T38 |
60 |
one_byte |
5430 |
1 |
|
|
T3 |
74 |
|
T8 |
37 |
|
T38 |
67 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
325898 |
1 |
|
|
T3 |
2839 |
|
T7 |
599 |
|
T8 |
1090 |
auto[1] |
6592 |
1 |
|
|
T3 |
44 |
|
T7 |
24 |
|
T8 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332490 |
1 |
|
|
T3 |
2883 |
|
T7 |
623 |
|
T8 |
1100 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332457 |
1 |
|
|
T3 |
2883 |
|
T7 |
623 |
|
T8 |
1100 |
auto[1] |
33 |
1 |
|
|
T14 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2368 |
1 |
|
|
T3 |
10 |
|
T7 |
12 |
|
T8 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6592 |
1 |
|
|
T3 |
44 |
|
T7 |
24 |
|
T8 |
10 |