Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

261016854

1

T1

32

T2

40231

T3

321686

full_word

185056935

1

T1

218

T2

44096

T3

316518

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	446073529	1			T1	250		T2	84327		T3	638204
auto[TlIntgErrCmd]	96	1			T120	4		T121	2		T122	7
auto[TlIntgErrData]	79	1			T120	4		T121	4		T122	3
auto[TlIntgErrBoth]	85	1			T120	2		T121	4		T122	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229198197

1

T1

101

T2

59061

T3

390979

auto[1]

216875592

1

T1

149

T2

25266

T3

247225

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157756470	1			T1	11		T2	29434		T3	248196
auto[TlIntgErrNone]	partial	auto[1]	103260156	1			T1	21		T2	10797		T3	73490
auto[TlIntgErrNone]	full_word	auto[0]	71441613	1			T1	90		T2	29627		T3	142783
auto[TlIntgErrNone]	full_word	auto[1]	113615290	1			T1	128		T2	14469		T3	173735
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T120	1		T122	3		T168	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T120	3		T121	2		T122	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T122	2		T172	1		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T168	1		T174	1		T175	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T120	3		T121	3		T122	1
auto[TlIntgErrData]	partial	auto[1]	33	1			T120	1		T121	1		T122	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T172	1		T171	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T173	1		T174	1		T176	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1			T121	1		T122	1		T168	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T120	2		T121	2		T122	7
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T122	1		T177	1		T178	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T121	1		T122	1		T177	1