Unified Coverage Report :: Module :: prim_sec_anchor_buf

Module : prim_sec_anchor_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak.u_prim_sec_anchor_buf
tb.dut.u_app_intf.u_prim_buf_state_output_sel
tb.dut.u_app_intf.u_prim_buf_state_err_check
tb.dut.u_app_intf.u_prim_buf_state_kmac_sel
tb.dut.u_app_intf.u_prim_buf_state_output_valid
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[3].u_prim_buf

---

Module Instance : tb.dut.u_sha3.u_keccak.u_prim_sec_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.81	94.55	100.00		73.33	91.18	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_prim_buf_state_output_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.15	94.57	86.30		48.89	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_prim_buf_state_err_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.15	94.57	86.30		48.89	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_prim_buf_state_kmac_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.15	94.57	86.30		48.89	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_app_intf.u_prim_buf_state_output_valid

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.15	94.57	86.30		48.89	91.01	100.00	u_app_intf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[4].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[5].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00