Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	876989	0	0
entropy_period_rd_A	2147483647	2259	0	0
intr_enable_rd_A	2147483647	3088	0	0
prefix_0_rd_A	2147483647	2093	0	0
prefix_10_rd_A	2147483647	2108	0	0
prefix_1_rd_A	2147483647	2054	0	0
prefix_2_rd_A	2147483647	1956	0	0
prefix_3_rd_A	2147483647	2043	0	0
prefix_4_rd_A	2147483647	2113	0	0
prefix_5_rd_A	2147483647	2139	0	0
prefix_6_rd_A	2147483647	2098	0	0
prefix_7_rd_A	2147483647	2073	0	0
prefix_8_rd_A	2147483647	2173	0	0
prefix_9_rd_A	2147483647	2125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	876989	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	17340	0	0
T58	363692	19178	0	0
T59	0	62136	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	43293	0	0
T126	0	86362	0	0
T127	0	40563	0	0
T128	0	43079	0	0
T129	0	74785	0	0
T130	0	46921	0	0
T131	0	95612	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2259	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	77	0	0
T58	363692	72	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	97	0	0
T92	0	9	0	0
T127	0	53	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	47	0	0
T150	0	55	0	0
T151	0	3	0	0
T152	0	241	0	0
T153	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3088	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	64	0	0
T58	363692	41	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	149	0	0
T92	0	11	0	0
T125	0	30	0	0
T127	0	38	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	43	0	0
T150	0	29	0	0
T154	0	10	0	0
T155	0	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2093	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	66	0	0
T58	363692	68	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	110	0	0
T92	0	7	0	0
T127	0	35	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	30	0	0
T150	0	8	0	0
T151	0	7	0	0
T152	0	488	0	0
T156	0	10	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2108	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	63	0	0
T58	363692	59	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	124	0	0
T92	0	15	0	0
T127	0	25	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	68	0	0
T150	0	25	0	0
T151	0	7	0	0
T152	0	454	0	0
T153	0	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2054	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	60	0	0
T58	363692	60	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	123	0	0
T92	0	10	0	0
T127	0	46	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	71	0	0
T150	0	17	0	0
T151	0	4	0	0
T152	0	451	0	0
T156	0	3	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1956	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	54	0	0
T58	363692	47	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	107	0	0
T92	0	9	0	0
T127	0	49	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	53	0	0
T150	0	30	0	0
T151	0	7	0	0
T152	0	419	0	0
T156	0	10	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2043	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	46	0	0
T58	363692	65	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	118	0	0
T92	0	9	0	0
T127	0	62	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	54	0	0
T150	0	29	0	0
T151	0	1	0	0
T152	0	441	0	0
T156	0	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2113	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	60	0	0
T58	363692	79	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	102	0	0
T92	0	11	0	0
T127	0	38	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	54	0	0
T150	0	19	0	0
T151	0	1	0	0
T152	0	416	0	0
T156	0	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2139	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	69	0	0
T58	363692	88	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	124	0	0
T92	0	15	0	0
T127	0	47	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	80	0	0
T150	0	25	0	0
T151	0	4	0	0
T152	0	477	0	0
T153	0	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2098	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	75	0	0
T58	363692	52	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	117	0	0
T92	0	15	0	0
T127	0	38	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	31	0	0
T150	0	55	0	0
T151	0	4	0	0
T152	0	380	0	0
T156	0	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2073	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	54	0	0
T58	363692	71	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	123	0	0
T92	0	17	0	0
T127	0	63	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	72	0	0
T150	0	42	0	0
T151	0	2	0	0
T152	0	414	0	0
T156	0	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2173	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	67	0	0
T58	363692	81	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	117	0	0
T92	0	18	0	0
T127	0	49	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	44	0	0
T150	0	13	0	0
T151	0	8	0	0
T152	0	442	0	0
T153	0	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T19	141217	0	0	0
T20	124424	0	0	0
T21	0	54	0	0
T58	363692	70	0	0
T69	445210	0	0	0
T79	1717	0	0	0
T81	0	136	0	0
T92	0	19	0	0
T127	0	74	0	0
T132	528245	0	0	0
T133	10187	0	0	0
T134	327113	0	0	0
T135	720	0	0	0
T136	316575	0	0	0
T149	0	27	0	0
T150	0	56	0	0
T151	0	7	0	0
T152	0	434	0	0
T157	0	5	0	0