Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174300 |
1 |
|
|
T1 |
291 |
|
T7 |
1476 |
|
T4 |
2708 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86013 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
68045 |
1 |
|
|
T1 |
10 |
|
T7 |
40 |
|
T4 |
2662 |
seven_bytes |
2886 |
1 |
|
|
T1 |
8 |
|
T7 |
45 |
|
T17 |
22 |
six_bytes |
2975 |
1 |
|
|
T1 |
8 |
|
T7 |
41 |
|
T17 |
24 |
five_bytes |
2928 |
1 |
|
|
T1 |
7 |
|
T7 |
45 |
|
T17 |
13 |
four_bytes |
2912 |
1 |
|
|
T1 |
8 |
|
T7 |
35 |
|
T17 |
15 |
three_bytes |
2890 |
1 |
|
|
T1 |
9 |
|
T7 |
39 |
|
T17 |
12 |
two_bytes |
2844 |
1 |
|
|
T1 |
6 |
|
T7 |
39 |
|
T17 |
14 |
one_byte |
2807 |
1 |
|
|
T1 |
7 |
|
T7 |
38 |
|
T17 |
16 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170852 |
1 |
|
|
T1 |
289 |
|
T7 |
1456 |
|
T4 |
2616 |
auto[1] |
3448 |
1 |
|
|
T1 |
2 |
|
T7 |
20 |
|
T4 |
92 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174300 |
1 |
|
|
T1 |
291 |
|
T7 |
1476 |
|
T4 |
2708 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174286 |
1 |
|
|
T1 |
291 |
|
T7 |
1476 |
|
T4 |
2708 |
auto[1] |
14 |
1 |
|
|
T116 |
1 |
|
T186 |
1 |
|
T187 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1234 |
1 |
|
|
T7 |
3 |
|
T4 |
46 |
|
T19 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3448 |
1 |
|
|
T1 |
2 |
|
T7 |
20 |
|
T4 |
92 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178177 |
1 |
|
|
T1 |
63 |
|
T7 |
3176 |
|
T4 |
2835 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87828 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
69671 |
1 |
|
|
T1 |
3 |
|
T7 |
76 |
|
T4 |
2788 |
seven_bytes |
2974 |
1 |
|
|
T7 |
94 |
|
T17 |
17 |
|
T37 |
37 |
six_bytes |
2875 |
1 |
|
|
T1 |
2 |
|
T7 |
85 |
|
T17 |
16 |
five_bytes |
2914 |
1 |
|
|
T1 |
3 |
|
T7 |
90 |
|
T17 |
15 |
four_bytes |
3011 |
1 |
|
|
T1 |
2 |
|
T7 |
87 |
|
T17 |
12 |
three_bytes |
2899 |
1 |
|
|
T1 |
1 |
|
T7 |
80 |
|
T17 |
9 |
two_bytes |
3074 |
1 |
|
|
T1 |
2 |
|
T7 |
88 |
|
T17 |
18 |
one_byte |
2931 |
1 |
|
|
T1 |
1 |
|
T7 |
81 |
|
T17 |
22 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174689 |
1 |
|
|
T1 |
61 |
|
T7 |
3140 |
|
T4 |
2741 |
auto[1] |
3488 |
1 |
|
|
T1 |
2 |
|
T7 |
36 |
|
T4 |
94 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178177 |
1 |
|
|
T1 |
63 |
|
T7 |
3176 |
|
T4 |
2835 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
178170 |
1 |
|
|
T1 |
63 |
|
T7 |
3176 |
|
T4 |
2834 |
auto[1] |
7 |
1 |
|
|
T4 |
1 |
|
T188 |
1 |
|
T144 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1250 |
1 |
|
|
T7 |
5 |
|
T4 |
47 |
|
T19 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3488 |
1 |
|
|
T1 |
2 |
|
T7 |
36 |
|
T4 |
94 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
346478 |
1 |
|
|
T1 |
13 |
|
T7 |
2945 |
|
T4 |
5587 |
auto[1] |
626 |
1 |
|
|
T4 |
89 |
|
T8 |
88 |
|
T9 |
37 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
175656 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
129554 |
1 |
|
|
T7 |
85 |
|
T4 |
5587 |
|
T19 |
274 |
seven_bytes |
5931 |
1 |
|
|
T7 |
91 |
|
T17 |
39 |
|
T37 |
43 |
six_bytes |
5980 |
1 |
|
|
T7 |
68 |
|
T17 |
52 |
|
T37 |
36 |
five_bytes |
6116 |
1 |
|
|
T1 |
1 |
|
T7 |
91 |
|
T17 |
48 |
four_bytes |
5868 |
1 |
|
|
T1 |
1 |
|
T7 |
80 |
|
T17 |
42 |
three_bytes |
6108 |
1 |
|
|
T7 |
80 |
|
T17 |
32 |
|
T37 |
56 |
two_bytes |
5965 |
1 |
|
|
T1 |
1 |
|
T7 |
73 |
|
T17 |
31 |
one_byte |
5926 |
1 |
|
|
T7 |
86 |
|
T17 |
46 |
|
T37 |
43 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
340342 |
1 |
|
|
T1 |
11 |
|
T7 |
2893 |
|
T4 |
5498 |
auto[1] |
6762 |
1 |
|
|
T1 |
2 |
|
T7 |
52 |
|
T4 |
178 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347104 |
1 |
|
|
T1 |
13 |
|
T7 |
2945 |
|
T4 |
5676 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347076 |
1 |
|
|
T1 |
13 |
|
T7 |
2945 |
|
T4 |
5676 |
auto[1] |
28 |
1 |
|
|
T79 |
1 |
|
T186 |
1 |
|
T189 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2387 |
1 |
|
|
T7 |
13 |
|
T4 |
89 |
|
T19 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6762 |
1 |
|
|
T1 |
2 |
|
T7 |
52 |
|
T4 |
178 |