Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262889376

1

T1

4048

T2

3949

T3

114011

full_word

186151418

1

T1

6586

T2

17727

T3

809280

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449040494	1			T1	10634		T2	21676		T3	194939
auto[TlIntgErrCmd]	114	1			T137	8		T138	2		T139	7
auto[TlIntgErrData]	91	1			T137	5		T138	6		T139	7
auto[TlIntgErrBoth]	95	1			T137	7		T138	2		T139	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231910372

1

T1

7307

T2

12851

T3

101992

auto[1]

217130422

1

T1

3327

T2

8825

T3

929467

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159813856	1			T1	2680		T2	2267		T3	700430
auto[TlIntgErrNone]	partial	auto[1]	103075250	1			T1	1368		T2	1682		T3	439680
auto[TlIntgErrNone]	full_word	auto[0]	72096375	1			T1	4627		T2	10584		T3	319493
auto[TlIntgErrNone]	full_word	auto[1]	114055013	1			T1	1959		T2	7143		T3	489787
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T137	2		T139	2		T190	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T137	5		T138	1		T139	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T195	1		T196	1		T197	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T137	1		T138	1		T198	2
auto[TlIntgErrData]	partial	auto[0]	41	1			T138	4		T139	2		T190	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T137	2		T138	1		T139	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T137	1		T138	1		T198	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T137	2		T139	1		T199	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T137	1		T138	2		T139	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T137	4		T139	3		T190	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T137	2		T139	1		T192	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T200	1		T201	3		T193	1