Unified Coverage Report :: Module :: kmac_entropy

Module : kmac_entropy

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.57	100.00	87.83		80.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_entropy.u_entropy	97.57	100.00	87.83		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_entropy.u_entropy

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.57	100.00	87.83		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	87.97	100.00	100.00	98.98	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_entropy_configured	100.00	100.00				100.00	100.00
u_hash_count	100.00			100.00
u_prim_trivium	95.62	100.00	88.37			94.12	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
TOTAL		968	968	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	340	6	6	100.00
ALWAYS	346	4	4	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
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CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
ALWAYS	391	4	4	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	3	3	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	422	3	3	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
ALWAYS	437	6	6	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	468	3	3	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	487	3	3	100.00
ALWAYS	492	86	86	100.00
CONT_ASSIGN	742	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	1	1
242	1	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
295	1	1
304	2	2
305	1	1
308	1	1
311	1	1
314	1	1
337	1	1
340	2	2
341	2	2
342	2	2
			MISSING_ELSE
346	2	2
347	2	2
			MISSING_ELSE
353	1	1
385	800	800
391	1	1
392	1	1
393	1	1
394	1	1
			MISSING_ELSE
399	1	1
404	1	1
407	1	1
408	1	1
410	1	1
417	1	1
422	1	1
423	1	1
425	1	1
432	1	1
433	1	1
437	1	1
438	1	1
439	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
447	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
478	1	1
487	3	3
492	1	1
493	1	1
496	1	1
497	1	1
499	1	1
507	1	1
508	1	1
511	1	1
514	1	1
515	1	1
516	1	1
519	1	1
520	1	1
521	1	1
524	1	1
526	1	1
528	1	1
531	1	1
533	1	1
535	1	1
538	1	1
539	1	1
544	1	1
545	1	1
548	1	1
558	1	1
563	1	1
568	1	1
570	1	1
572	1	1
578	1	1
579	1	1
581	1	1
582	1	1
584	1	1
586	1	1
588	1	1
591	1	1
592	1	1
595	1	1
598	1	1
600	1	1
606	1	1
609	1	1
611	1	1
613	1	1
615	1	1
616	1	1
618	1	1
619	1	1
621	1	1
622	1	1
623	1	1
624	1	1
			MISSING_ELSE
627	1	1
629	1	1
636	1	1
638	1	1
639	1	1
640	1	1
642	1	1
648	1	1
650	1	1
651	1	1
653	1	1
654	1	1
656	1	1
658	1	1
676	1	1
677	1	1
678	1	1
680	1	1
684	1	1
686	1	1
693	1	1
695	1	1
703	1	1
706	1	1
708	1	1
710	1	1
711	1	1
714	1	1
721	1	1
722	1	1
734	1	1
735	1	1
			MISSING_ELSE
742	1	1

---

Cond Coverage for Module : kmac_entropy

	Total	Covered	Percent
Conditions	115	101	87.83
Logical	115	101	87.83
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T34,T48,T18
1	1	0	Covered	T1,T3,T7
1	1	1	Covered	T34,T48,T40

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T48,T40
1	1	Covered	T1,T2,T3

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T34,T48,T40
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T32,T34
1	1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T32,T34
1	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T32,T34
1	1	Covered	T1,T2,T3

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T17,T37
0	1	0	Covered	T7,T38,T79
1	0	0	Covered	T1,T7,T17

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       337
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T17
1	1	Covered	T7,T38,T79

 LINE       353
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       353
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       364
 EXPRESSION (prng_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (data_update || msg_mask_en_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       404
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       417
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 2)-:4] : ({1'b0, prng_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T40,T41,T80
1	0	Covered	T2,T32,T34

 LINE       466
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T32,T34
1	1	Covered	T2,T32,T34

 LINE       466
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T32,T34
1	0	Covered	T40,T41,T80

 LINE       572
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       572
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       588
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T37
1	0	Covered	T2,T32,T34
1	1	Covered	T38,T79,T15

 LINE       588
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T2,T32,T34

 LINE       588
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T38,T79
1	0	Covered	T17,T37,T38

 LINE       611
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T48,T40
1	0	Covered	T2,T32,T35
1	1	Covered	T40,T41,T80

 LINE       615
 EXPRESSION (entropy_req_o && entropy_ack_i)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T32,T34
1	1	Covered	T2,T32,T34

 LINE       621
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T18,T38
0	1	Covered	T2,T32,T35
1	0	Covered	T81,T82,T83

 LINE       621
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T18,T38
1	1	Covered	T81,T82,T83

 LINE       629
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T35
1	0	Covered	T38,T84,T85
1	1	Covered	T38,T79,T86

 LINE       629
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T32,T34
0	1	Not Covered
1	0	Covered	T38,T79,T84

 LINE       629
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T18,T38
0	1	Covered	T2,T32,T35
1	0	Covered	T81,T82,T83

 LINE       629
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T18,T38
1	1	Covered	T81,T82,T83

 LINE       648
 EXPRESSION (seed_req & seed_update_i)
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       706
 EXPRESSION ((rand_update_i | rand_consumed_i) & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             ----------------1----------------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T87
1	0	Not Covered
1	1	Not Covered

 LINE       706
 SUB-EXPRESSION (rand_update_i | rand_consumed_i)
                 ------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T87
0	1	Not Covered
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T87,T88,T89
0	1	Covered	T40,T41,T87
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T87,T88,T89
1	1	Not Covered

 LINE       742
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : kmac_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	20	16	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	545	Covered	T2,T32,T34
StRandErr	684	Covered	T40,T41,T87
StRandErrIncorrectMode	554	Covered	T87,T88,T89
StRandErrWaitExpired	613	Covered	T40,T41,T80
StRandGenerate	582	Covered	T1,T2,T3
StRandReady	586	Covered	T1,T2,T3
StRandReset	558	Covered	T1,T2,T3
StSwSeedWait	539	Covered	T1,T3,T7
StTerminalError	735	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
StRandEdn->StRandErrWaitExpired	613	Covered	T40,T41,T80
StRandEdn->StRandGenerate	619	Covered	T2,T32,T34
StRandEdn->StTerminalError	735	Covered	T90
StRandErr->StRandReset	711	Covered	T40,T41,T87
StRandErr->StTerminalError	735	Not Covered
StRandErrIncorrectMode->StRandErr	693	Covered	T87,T88,T89
StRandErrIncorrectMode->StTerminalError	735	Not Covered
StRandErrWaitExpired->StRandErr	684	Covered	T40,T41,T80
StRandErrWaitExpired->StTerminalError	735	Not Covered
StRandGenerate->StRandReady	680	Covered	T1,T2,T3
StRandGenerate->StTerminalError	735	Covered	T57,T58,T59
StRandReady->StRandEdn	592	Covered	T38,T79,T15
StRandReady->StRandGenerate	582	Covered	T1,T2,T3
StRandReady->StTerminalError	735	Covered	T10,T11,T12
StRandReset->StRandEdn	545	Covered	T2,T32,T34
StRandReset->StRandErrIncorrectMode	554	Covered	T87,T88,T89
StRandReset->StSwSeedWait	539	Covered	T1,T3,T7
StRandReset->StTerminalError	735	Covered	T27,T28,T29
StSwSeedWait->StRandGenerate	651	Covered	T1,T3,T7
StSwSeedWait->StTerminalError	735	Not Covered

---

Branch Coverage for Module : kmac_entropy

	Line No.	Total	Covered	Percent
Branches		77	77	100.00
TERNARY	353	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	417	2	2	100.00
TERNARY	742	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	340	4	4	100.00
IF	346	3	3	100.00
IF	391	3	3	100.00
IF	407	2	2	100.00
IF	422	2	2	100.00
IF	437	4	4	100.00
IF	468	2	2	100.00
IF	487	2	2	100.00
CASE	526	23	23	100.00
IF	734	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	353	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	404	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	417	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	742	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T32,T34
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T34,T48,T40
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T32,T34
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T32,T34
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T32,T34
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	340	if ((!rst_ni))
-2-:	341	if (threshold_hit_clr)
-3-:	342	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T38,T79,T15
0	0	1	Covered	T7,T38,T79
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	347	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	if ((!rst_ni))
-2-:	393	if ((data_update || msg_mask_en_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	407	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	422	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))
-2-:	439	if (rand_valid_set)
-3-:	441	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	468	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	526	case (st)
-2-:	528	if (entropy_ready_i)
-3-:	535	case (mode_i)
-4-:	572	if (((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	581	if (rand_consumed_i)
-6-:	588	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	611	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	615	if ((entropy_req_o && entropy_ack_i))
-9-:	618	if (seed_done)
-10-:	621	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	629	if (((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	650	if (seed_done)
-13-:	710	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T2,T32,T34
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T87,T88,T89
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T38,T79,T15
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T41,T80
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T2,T32,T35
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T34,T18,T38
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T2,T32,T34
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T38,T79,T86
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T2,T32,T34
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T7
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T7
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T41,T80
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T87,T88,T89
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T40,T41,T87
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T40,T41,T87
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	734	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ConsumeNotAssertWhenNotValid_M	2147483647	232446364	0	0
EdnBusWidth_A	1020	1020	0	0
ModeKnown_A	2147483647	2147483647	0	0
RandStKnown_A	2147483647	2147483647	0	0
p_perm_check.PermutationCheck_A	1020	1020	0	0
u_state_regs_A	2147483647	2147483647	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	232446364	0	0
T1	101713	7344	0	0
T2	310124	25272	0	0
T3	513745	975600	0	0
T4	497729	31320	0	0
T7	146617	99936	0	0
T32	190914	397872	0	0
T33	10752	2232	0	0
T34	596464	946584	0	0
T35	11866	2232	0	0
T36	142602	551304	0	0

EdnBusWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1020	1020	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101713	101642	0	0
T2	310124	310051	0	0
T3	513745	513740	0	0
T4	497729	497678	0	0
T7	146617	146608	0	0
T32	190914	190906	0	0
T33	10752	10686	0	0
T34	596464	596456	0	0
T35	11866	11810	0	0
T36	142602	142596	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101713	101642	0	0
T2	310124	310051	0	0
T3	513745	513740	0	0
T4	497729	497678	0	0
T7	146617	146608	0	0
T32	190914	190906	0	0
T33	10752	10686	0	0
T34	596464	596456	0	0
T35	11866	11810	0	0
T36	142602	142596	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1020	1020	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101713	101642	0	0
T2	310124	310051	0	0
T3	513745	513740	0	0
T4	497729	497678	0	0
T7	146617	146608	0	0
T32	190914	190906	0	0
T33	10752	10686	0	0
T34	596464	596456	0	0
T35	11866	11810	0	0
T36	142602	142596	0	0

Line Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
TOTAL		968	968	100.00
ALWAYS	241	4	4	100.00
ALWAYS	250	4	4	100.00
ALWAYS	259	8	8	100.00
CONT_ASSIGN	270	1	1	100.00
ALWAYS	273	6	6	100.00
ALWAYS	284	8	8	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	304	3	3	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
ALWAYS	340	6	6	100.00
ALWAYS	346	4	4	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
ALWAYS	391	4	4	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
ALWAYS	407	3	3	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	422	3	3	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
ALWAYS	437	6	6	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
ALWAYS	468	3	3	100.00
CONT_ASSIGN	478	1	1	100.00
ALWAYS	487	3	3	100.00
ALWAYS	492	86	86	100.00
CONT_ASSIGN	742	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
241	1	1
242	1	1
243	1	1
244	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
			MISSING_ELSE
259	1	1
260	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
			MISSING_ELSE
270	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
			MISSING_ELSE
295	1	1
304	2	2
305	1	1
308	1	1
311	1	1
314	1	1
337	1	1
340	2	2
341	2	2
342	2	2
			MISSING_ELSE
346	2	2
347	2	2
			MISSING_ELSE
353	1	1
385	800	800
391	1	1
392	1	1
393	1	1
394	1	1
			MISSING_ELSE
399	1	1
404	1	1
407	1	1
408	1	1
410	1	1
417	1	1
422	1	1
423	1	1
425	1	1
432	1	1
433	1	1
437	1	1
438	1	1
439	1	1
440	1	1
441	1	1
442	1	1
			MISSING_ELSE
447	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
478	1	1
487	3	3
492	1	1
493	1	1
496	1	1
497	1	1
499	1	1
507	1	1
508	1	1
511	1	1
514	1	1
515	1	1
516	1	1
519	1	1
520	1	1
521	1	1
524	1	1
526	1	1
528	1	1
531	1	1
533	1	1
535	1	1
538	1	1
539	1	1
544	1	1
545	1	1
548	1	1
558	1	1
563	1	1
568	1	1
570	1	1
572	1	1
578	1	1
579	1	1
581	1	1
582	1	1
584	1	1
586	1	1
588	1	1
591	1	1
592	1	1
595	1	1
598	1	1
600	1	1
606	1	1
609	1	1
611	1	1
613	1	1
615	1	1
616	1	1
618	1	1
619	1	1
621	1	1
622	1	1
623	1	1
624	1	1
			MISSING_ELSE
627	1	1
629	1	1
636	1	1
638	1	1
639	1	1
640	1	1
642	1	1
648	1	1
650	1	1
651	1	1
653	1	1
654	1	1
656	1	1
658	1	1
676	1	1
677	1	1
678	1	1
680	1	1
684	1	1
686	1	1
693	1	1
695	1	1
703	1	1
706	1	1
708	1	1
710	1	1
711	1	1
714	1	1
721	1	1
722	1	1
734	1	1
735	1	1
			MISSING_ELSE
742	1	1

---

Cond Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Covered	Percent
Conditions	115	101	87.83
Logical	115	101	87.83
Non-Logical	0	0
Event	0	0

 LINE       265
 EXPRESSION (timer_enable && timer_pulse && ((|timer_value)))
             ------1-----    -----2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T34,T48,T18
1	1	0	Covered	T1,T3,T7
1	1	1	Covered	T34,T48,T40

 LINE       277
 EXPRESSION (timer_enable && (timer_value == '0))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T48,T40
1	1	Covered	T1,T2,T3

 LINE       277
 SUB-EXPRESSION (timer_value == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T34,T48,T40
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T32,T34
1	1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T32,T34
1	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (timer_enable && (prescaler_cnt == '0))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T32,T34
1	1	Covered	T1,T2,T3

 LINE       295
 SUB-EXPRESSION (prescaler_cnt == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       311
 EXPRESSION (hash_cnt_clr_i || threshold_hit || entropy_refresh_req_i)
             -------1------    ------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T7,T17,T37
0	1	0	Covered	T7,T38,T79
1	0	0	Covered	T1,T7,T17

 LINE       314
 EXPRESSION (hash_progress_q && ((!hash_progress_d)))
             -------1-------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       337
 EXPRESSION (((|hash_threshold_i)) && (hash_threshold_i <= hash_cnt_o))
             ----------1----------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T17
1	1	Covered	T7,T38,T79

 LINE       353
 EXPRESSION ((mode_q == EntropyModeSw) ? seed_data_i : entropy_data_i)
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       353
 SUB-EXPRESSION (mode_q == EntropyModeSw)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T7

 LINE       364
 EXPRESSION (prng_en || msg_mask_en_i)
             ---1---    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (data_update || msg_mask_en_i)
             -----1-----    ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       404
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 1)] : aux_rand_q)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       417
 EXPRESSION (aux_update ? rand_data_q[(kmac_pkg::EntropyOutputW - 2)-:4] : ({1'b0, prng_en_rand_q[3:1]}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       465
 EXPRESSION (entropy_req | entropy_req_hold_q)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T40,T41,T80
1	0	Covered	T2,T32,T34

 LINE       466
 EXPRESSION ((entropy_req_hold_q | entropy_req) & ((~entropy_ack_i)))
             -----------------1----------------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T32,T34
1	1	Covered	T2,T32,T34

 LINE       466
 SUB-EXPRESSION (entropy_req_hold_q | entropy_req)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T32,T34
1	0	Covered	T40,T41,T80

 LINE       572
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       572
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       572
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       588
 EXPRESSION ((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q))
             -------------1------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T17,T37
1	0	Covered	T2,T32,T34
1	1	Covered	T38,T79,T15

 LINE       588
 SUB-EXPRESSION (mode_q == EntropyModeEdn)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T2,T32,T34

 LINE       588
 SUB-EXPRESSION (entropy_refresh_req_i || threshold_hit_q)
                 ----------1----------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T38,T79
1	0	Covered	T17,T37,T38

 LINE       611
 EXPRESSION (timer_expired && non_zero_wait_timer_limit)
             ------1------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T48,T40
1	0	Covered	T2,T32,T35
1	1	Covered	T40,T41,T80

 LINE       615
 EXPRESSION (entropy_req_o && entropy_ack_i)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T32,T34
1	1	Covered	T2,T32,T34

 LINE       621
 EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
             ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T18,T38
0	1	Covered	T2,T32,T35
1	0	Covered	T81,T82,T83

 LINE       621
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T18,T38
1	1	Covered	T81,T82,T83

 LINE       629
 EXPRESSION ((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || ((!fast_process_i))))
             -----------------1----------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T35
1	0	Covered	T38,T84,T85
1	1	Covered	T38,T79,T86

 LINE       629
 SUB-EXPRESSION (rand_update_i || rand_consumed_i)
                 ------1------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T32,T34
0	1	Not Covered
1	0	Covered	T38,T79,T84

 LINE       629
 SUB-EXPRESSION ((fast_process_i && in_keyblock_i) || ((!fast_process_i)))
                 ----------------1----------------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T18,T38
0	1	Covered	T2,T32,T35
1	0	Covered	T81,T82,T83

 LINE       629
 SUB-EXPRESSION (fast_process_i && in_keyblock_i)
                 -------1------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T34,T18,T38
1	1	Covered	T81,T82,T83

 LINE       648
 EXPRESSION (seed_req & seed_update_i)
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       706
 EXPRESSION ((rand_update_i | rand_consumed_i) & ((fast_process_i & in_keyblock_i) | ((~fast_process_i))))
             ----------------1----------------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T87
1	0	Not Covered
1	1	Not Covered

 LINE       706
 SUB-EXPRESSION (rand_update_i | rand_consumed_i)
                 ------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T87
0	1	Not Covered
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION ((fast_process_i & in_keyblock_i) | ((~fast_process_i)))
                 ----------------1---------------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T87,T88,T89
0	1	Covered	T40,T41,T87
1	0	Not Covered

 LINE       706
 SUB-EXPRESSION (fast_process_i & in_keyblock_i)
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T87,T88,T89
1	1	Not Covered

 LINE       742
 EXPRESSION ((st != StRandReset) ? MuBi4True : MuBi4False)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       742
 SUB-EXPRESSION (st != StRandReset)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_entropy.u_entropy

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	16	16	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StRandEdn	545	Covered	T2,T32,T34
StRandErr	684	Covered	T40,T41,T87
StRandErrIncorrectMode	554	Covered	T87,T88,T89
StRandErrWaitExpired	613	Covered	T40,T41,T80
StRandGenerate	582	Covered	T1,T2,T3
StRandReady	586	Covered	T1,T2,T3
StRandReset	558	Covered	T1,T2,T3
StSwSeedWait	539	Covered	T1,T3,T7
StTerminalError	735	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests	Exclude Annotation
StRandEdn->StRandErrWaitExpired	613	Covered	T40,T41,T80
StRandEdn->StRandGenerate	619	Covered	T2,T32,T34
StRandEdn->StTerminalError	735	Covered	T90
StRandErr->StRandReset	711	Covered	T40,T41,T87
StRandErr->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrIncorrectMode->StRandErr	693	Covered	T87,T88,T89
StRandErrIncorrectMode->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandErrWaitExpired->StRandErr	684	Covered	T40,T41,T80
StRandErrWaitExpired->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StRandGenerate->StRandReady	680	Covered	T1,T2,T3
StRandGenerate->StTerminalError	735	Covered	T57,T58,T59
StRandReady->StRandEdn	592	Covered	T38,T79,T15
StRandReady->StRandGenerate	582	Covered	T1,T2,T3
StRandReady->StTerminalError	735	Covered	T10,T11,T12
StRandReset->StRandEdn	545	Covered	T2,T32,T34
StRandReset->StRandErrIncorrectMode	554	Covered	T87,T88,T89
StRandReset->StSwSeedWait	539	Covered	T1,T3,T7
StRandReset->StTerminalError	735	Covered	T27,T28,T29
StSwSeedWait->StRandGenerate	651	Covered	T1,T3,T7
StSwSeedWait->StTerminalError	735	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Line No.	Total	Covered	Percent
Branches		77	77	100.00
TERNARY	353	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	417	2	2	100.00
TERNARY	742	2	2	100.00
IF	241	3	3	100.00
IF	250	3	3	100.00
IF	259	5	5	100.00
IF	273	4	4	100.00
IF	284	5	5	100.00
IF	304	2	2	100.00
IF	340	4	4	100.00
IF	346	3	3	100.00
IF	391	3	3	100.00
IF	407	2	2	100.00
IF	422	2	2	100.00
IF	437	4	4	100.00
IF	468	2	2	100.00
IF	487	2	2	100.00
CASE	526	23	23	100.00
IF	734	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_entropy.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	353	((mode_q == EntropyModeSw)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	404	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	417	(aux_update) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	742	((st != StRandReset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	241	if ((!rst_ni))
-2-:	243	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	252	if (timer_update)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T32,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	259	if ((!rst_ni))
-2-:	261	if (timer_update)
-3-:	263	if (timer_expired)
-4-:	265	if (((timer_enable && timer_pulse) && (|timer_value)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T32,T34
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T34,T48,T40
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (timer_update)
-3-:	277	if ((timer_enable && (timer_value == '0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T32,T34
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	284	if ((!rst_ni))
-2-:	286	if (timer_update)
-3-:	288	if ((timer_enable && (prescaler_cnt == '0)))
-4-:	290	if (timer_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T32,T34
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T32,T34
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	304	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	340	if ((!rst_ni))
-2-:	341	if (threshold_hit_clr)
-3-:	342	if (threshold_hit)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T38,T79,T15
0	0	1	Covered	T7,T38,T79
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	347	if (mode_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	391	if ((!rst_ni))
-2-:	393	if ((data_update || msg_mask_en_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	407	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	422	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))
-2-:	439	if (rand_valid_set)
-3-:	441	if (rand_valid_clear)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	468	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	526	case (st)
-2-:	528	if (entropy_ready_i)
-3-:	535	case (mode_i)
-4-:	572	if (((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-5-:	581	if (rand_consumed_i)
-6-:	588	if (((mode_q == EntropyModeEdn) && (entropy_refresh_req_i || threshold_hit_q)))
-7-:	611	if ((timer_expired && non_zero_wait_timer_limit))
-8-:	615	if ((entropy_req_o && entropy_ack_i))
-9-:	618	if (seed_done)
-10-:	621	if (((fast_process_i && in_keyblock_i) || (!fast_process_i)))
-11-:	629	if (((rand_update_i || rand_consumed_i) && ((fast_process_i && in_keyblock_i) || (!fast_process_i))))
-12-:	650	if (seed_done)
-13-:	710	if (err_processed_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StRandReset	1	EntropyModeSw	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
StRandReset	1	EntropyModeEdn	-	-	-	-	-	-	-	-	-	-	Covered	T2,T32,T34
StRandReset	1	default	-	-	-	-	-	-	-	-	-	-	Covered	T87,T88,T89
StRandReset	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandReady	-	-	0	-	1	-	-	-	-	-	-	-	Covered	T38,T79,T15
StRandReady	-	-	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandEdn	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T41,T80
StRandEdn	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T2,T32,T35
StRandEdn	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T34,T18,T38
StRandEdn	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T2,T32,T34
StRandEdn	-	-	-	-	-	0	0	-	-	1	-	-	Covered	T38,T79,T86
StRandEdn	-	-	-	-	-	0	0	-	-	0	-	-	Covered	T2,T32,T34
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T7
StSwSeedWait	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T7
StRandGenerate	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRandErrWaitExpired	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T40,T41,T80
StRandErrIncorrectMode	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T87,T88,T89
StRandErr	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T40,T41,T87
StRandErr	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T40,T41,T87
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	734	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_entropy.u_entropy

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ConsumeNotAssertWhenNotValid_M	2147483647	232446364	0	0
EdnBusWidth_A	1020	1020	0	0
ModeKnown_A	2147483647	2147483647	0	0
RandStKnown_A	2147483647	2147483647	0	0
p_perm_check.PermutationCheck_A	1020	1020	0	0
u_state_regs_A	2147483647	2147483647	0	0

ConsumeNotAssertWhenNotValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	232446364	0	0
T1	101713	7344	0	0
T2	310124	25272	0	0
T3	513745	975600	0	0
T4	497729	31320	0	0
T7	146617	99936	0	0
T32	190914	397872	0	0
T33	10752	2232	0	0
T34	596464	946584	0	0
T35	11866	2232	0	0
T36	142602	551304	0	0

EdnBusWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1020	1020	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

ModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101713	101642	0	0
T2	310124	310051	0	0
T3	513745	513740	0	0
T4	497729	497678	0	0
T7	146617	146608	0	0
T32	190914	190906	0	0
T33	10752	10686	0	0
T34	596464	596456	0	0
T35	11866	11810	0	0
T36	142602	142596	0	0

RandStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101713	101642	0	0
T2	310124	310051	0	0
T3	513745	513740	0	0
T4	497729	497678	0	0
T7	146617	146608	0	0
T32	190914	190906	0	0
T33	10752	10686	0	0
T34	596464	596456	0	0
T35	11866	11810	0	0
T36	142602	142596	0	0

p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1020	1020	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	101713	101642	0	0
T2	310124	310051	0	0
T3	513745	513740	0	0
T4	497729	497678	0	0
T7	146617	146608	0	0
T32	190914	190906	0	0
T33	10752	10686	0	0
T34	596464	596456	0	0
T35	11866	11810	0	0
T36	142602	142596	0	0