Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	441911	0	0
entropy_period_rd_A	2147483647	2272	0	0
intr_enable_rd_A	2147483647	2854	0	0
prefix_0_rd_A	2147483647	2194	0	0
prefix_10_rd_A	2147483647	2207	0	0
prefix_1_rd_A	2147483647	1988	0	0
prefix_2_rd_A	2147483647	2267	0	0
prefix_3_rd_A	2147483647	2086	0	0
prefix_4_rd_A	2147483647	2245	0	0
prefix_5_rd_A	2147483647	2148	0	0
prefix_6_rd_A	2147483647	1999	0	0
prefix_7_rd_A	2147483647	2090	0	0
prefix_8_rd_A	2147483647	2161	0	0
prefix_9_rd_A	2147483647	2200	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	441911	0	0
T24	0	27487	0	0
T26	2367	0	0	0
T45	260492	32314	0	0
T46	0	44838	0	0
T57	2533	0	0	0
T91	0	9148	0	0
T92	0	18593	0	0
T93	0	21708	0	0
T143	0	24481	0	0
T144	0	90332	0	0
T145	0	47051	0	0
T146	0	62101	0	0
T147	179170	0	0	0
T148	519517	0	0	0
T149	1787	0	0	0
T150	331695	0	0	0
T151	475290	0	0	0
T152	102852	0	0	0
T153	18918	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2272	0	0
T78	56096	0	0	0
T91	133666	46	0	0
T92	0	89	0	0
T93	0	70	0	0
T109	0	4	0	0
T162	0	215	0	0
T163	0	7	0	0
T164	0	4	0	0
T165	0	97	0	0
T166	0	17	0	0
T167	0	14	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2854	0	0
T78	56096	0	0	0
T91	133666	39	0	0
T92	0	36	0	0
T93	0	74	0	0
T104	0	3	0	0
T162	0	503	0	0
T163	0	7	0	0
T164	0	6	0	0
T165	0	154	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T176	0	16	0	0
T177	0	16	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2194	0	0
T78	56096	0	0	0
T91	133666	28	0	0
T92	0	54	0	0
T93	0	66	0	0
T109	0	9	0	0
T162	0	516	0	0
T164	0	6	0	0
T165	0	99	0	0
T166	0	12	0	0
T167	0	24	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2207	0	0
T78	56096	0	0	0
T91	133666	37	0	0
T92	0	48	0	0
T93	0	56	0	0
T109	0	6	0	0
T162	0	492	0	0
T163	0	6	0	0
T164	0	6	0	0
T165	0	139	0	0
T166	0	1	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	1	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988	0	0
T78	56096	0	0	0
T91	133666	32	0	0
T92	0	41	0	0
T93	0	76	0	0
T109	0	4	0	0
T162	0	429	0	0
T164	0	16	0	0
T165	0	117	0	0
T166	0	4	0	0
T167	0	15	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2267	0	0
T78	56096	0	0	0
T91	133666	58	0	0
T92	0	56	0	0
T93	0	51	0	0
T104	0	2	0	0
T162	0	466	0	0
T163	0	4	0	0
T164	0	7	0	0
T165	0	94	0	0
T166	0	8	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	13	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2086	0	0
T78	56096	0	0	0
T91	133666	46	0	0
T92	0	44	0	0
T93	0	46	0	0
T109	0	10	0	0
T162	0	440	0	0
T164	0	9	0	0
T165	0	117	0	0
T166	0	6	0	0
T167	0	26	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2245	0	0
T78	56096	0	0	0
T91	133666	46	0	0
T92	0	43	0	0
T93	0	92	0	0
T104	0	5	0	0
T109	0	4	0	0
T162	0	407	0	0
T164	0	7	0	0
T165	0	97	0	0
T166	0	9	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2148	0	0
T78	56096	0	0	0
T91	133666	33	0	0
T92	0	31	0	0
T93	0	72	0	0
T104	0	8	0	0
T162	0	453	0	0
T163	0	4	0	0
T164	0	6	0	0
T165	0	106	0	0
T166	0	2	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1999	0	0
T78	56096	0	0	0
T91	133666	25	0	0
T92	0	62	0	0
T93	0	69	0	0
T104	0	3	0	0
T109	0	7	0	0
T162	0	463	0	0
T164	0	1	0	0
T165	0	80	0	0
T167	0	15	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2090	0	0
T78	56096	0	0	0
T91	133666	45	0	0
T92	0	48	0	0
T93	0	54	0	0
T109	0	1	0	0
T162	0	426	0	0
T163	0	9	0	0
T164	0	13	0	0
T165	0	97	0	0
T166	0	7	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T78	56096	0	0	0
T91	133666	18	0	0
T92	0	88	0	0
T93	0	85	0	0
T109	0	11	0	0
T162	0	434	0	0
T163	0	2	0	0
T164	0	9	0	0
T165	0	101	0	0
T166	0	6	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2200	0	0
T78	56096	0	0	0
T91	133666	37	0	0
T92	0	68	0	0
T93	0	72	0	0
T104	0	1	0	0
T162	0	485	0	0
T163	0	5	0	0
T164	0	7	0	0
T165	0	160	0	0
T166	0	7	0	0
T168	52754	0	0	0
T169	149742	0	0	0
T170	148853	0	0	0
T171	159573	0	0	0
T172	488506	0	0	0
T173	12753	0	0	0
T174	323628	0	0	0
T175	123539	0	0	0
T178	0	7	0	0