Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184799 |
1 |
|
|
T1 |
1037 |
|
T7 |
46 |
|
T8 |
33 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
93986 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
68606 |
1 |
|
|
T1 |
650 |
|
T7 |
44 |
|
T8 |
31 |
seven_bytes |
3231 |
1 |
|
|
T1 |
6 |
|
T15 |
6 |
|
T17 |
39 |
six_bytes |
3181 |
1 |
|
|
T1 |
12 |
|
T15 |
6 |
|
T17 |
30 |
five_bytes |
3144 |
1 |
|
|
T1 |
14 |
|
T15 |
14 |
|
T17 |
30 |
four_bytes |
3132 |
1 |
|
|
T1 |
15 |
|
T15 |
12 |
|
T17 |
29 |
three_bytes |
3107 |
1 |
|
|
T1 |
7 |
|
T15 |
11 |
|
T17 |
29 |
two_bytes |
3232 |
1 |
|
|
T1 |
10 |
|
T15 |
9 |
|
T17 |
38 |
one_byte |
3180 |
1 |
|
|
T1 |
14 |
|
T15 |
11 |
|
T17 |
19 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181282 |
1 |
|
|
T1 |
1013 |
|
T7 |
42 |
|
T8 |
29 |
auto[1] |
3517 |
1 |
|
|
T1 |
24 |
|
T7 |
4 |
|
T8 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184799 |
1 |
|
|
T1 |
1037 |
|
T7 |
46 |
|
T8 |
33 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184789 |
1 |
|
|
T1 |
1037 |
|
T7 |
46 |
|
T8 |
33 |
auto[1] |
10 |
1 |
|
|
T63 |
1 |
|
T165 |
1 |
|
T166 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1227 |
1 |
|
|
T1 |
10 |
|
T7 |
2 |
|
T8 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3517 |
1 |
|
|
T1 |
24 |
|
T7 |
4 |
|
T8 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177244 |
1 |
|
|
T1 |
1098 |
|
T8 |
511 |
|
T15 |
409 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
88141 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
68362 |
1 |
|
|
T1 |
652 |
|
T8 |
504 |
|
T15 |
40 |
seven_bytes |
3002 |
1 |
|
|
T1 |
9 |
|
T15 |
11 |
|
T17 |
16 |
six_bytes |
2964 |
1 |
|
|
T1 |
6 |
|
T15 |
8 |
|
T17 |
21 |
five_bytes |
3016 |
1 |
|
|
T1 |
8 |
|
T15 |
13 |
|
T17 |
29 |
four_bytes |
2953 |
1 |
|
|
T1 |
10 |
|
T15 |
14 |
|
T17 |
12 |
three_bytes |
2997 |
1 |
|
|
T1 |
15 |
|
T15 |
9 |
|
T17 |
27 |
two_bytes |
2928 |
1 |
|
|
T1 |
5 |
|
T15 |
11 |
|
T17 |
19 |
one_byte |
2881 |
1 |
|
|
T1 |
17 |
|
T15 |
8 |
|
T17 |
25 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173760 |
1 |
|
|
T1 |
1072 |
|
T8 |
497 |
|
T15 |
401 |
auto[1] |
3484 |
1 |
|
|
T1 |
26 |
|
T8 |
14 |
|
T15 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177244 |
1 |
|
|
T1 |
1098 |
|
T8 |
511 |
|
T15 |
409 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177231 |
1 |
|
|
T1 |
1098 |
|
T8 |
511 |
|
T15 |
409 |
auto[1] |
13 |
1 |
|
|
T9 |
1 |
|
T62 |
1 |
|
T167 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1242 |
1 |
|
|
T1 |
13 |
|
T8 |
7 |
|
T15 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3484 |
1 |
|
|
T1 |
26 |
|
T8 |
14 |
|
T15 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359483 |
1 |
|
|
T1 |
2765 |
|
T7 |
16 |
|
T8 |
773 |
auto[1] |
501 |
1 |
|
|
T9 |
53 |
|
T10 |
5 |
|
T11 |
21 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
184696 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
131342 |
1 |
|
|
T1 |
1323 |
|
T7 |
15 |
|
T8 |
759 |
seven_bytes |
6388 |
1 |
|
|
T1 |
45 |
|
T15 |
34 |
|
T17 |
68 |
six_bytes |
6242 |
1 |
|
|
T1 |
32 |
|
T15 |
33 |
|
T17 |
56 |
five_bytes |
6189 |
1 |
|
|
T1 |
35 |
|
T15 |
45 |
|
T17 |
58 |
four_bytes |
6409 |
1 |
|
|
T1 |
39 |
|
T15 |
27 |
|
T17 |
65 |
three_bytes |
6223 |
1 |
|
|
T1 |
45 |
|
T15 |
28 |
|
T17 |
57 |
two_bytes |
6334 |
1 |
|
|
T1 |
45 |
|
T15 |
26 |
|
T17 |
61 |
one_byte |
6161 |
1 |
|
|
T1 |
36 |
|
T15 |
27 |
|
T17 |
67 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
353028 |
1 |
|
|
T1 |
2717 |
|
T7 |
14 |
|
T8 |
745 |
auto[1] |
6956 |
1 |
|
|
T1 |
48 |
|
T7 |
2 |
|
T8 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359984 |
1 |
|
|
T1 |
2765 |
|
T7 |
16 |
|
T8 |
773 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359961 |
1 |
|
|
T1 |
2765 |
|
T7 |
16 |
|
T8 |
773 |
auto[1] |
23 |
1 |
|
|
T17 |
2 |
|
T16 |
1 |
|
T168 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2430 |
1 |
|
|
T1 |
20 |
|
T7 |
1 |
|
T8 |
14 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6956 |
1 |
|
|
T1 |
48 |
|
T7 |
2 |
|
T8 |
28 |