Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

269465804

1

T1

188796

T2

9638

T3

39626

full_word

189324778

1

T1

190772

T2

10141

T3

59298

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	458790282	1			T1	379568		T2	19779		T3	98924
auto[TlIntgErrCmd]	109	1			T126	5		T127	2		T128	6
auto[TlIntgErrData]	89	1			T126	10		T127	4		T128	2
auto[TlIntgErrBoth]	102	1			T126	5		T127	4		T128	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236244160

1

T1

243307

T2

14307

T3

65059

auto[1]

222546422

1

T1

136261

T2

5472

T3

33865

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	162873380	1			T1	142465		T2	6933		T3	25428
auto[TlIntgErrNone]	partial	auto[1]	106592149	1			T1	46331		T2	2705		T3	14198
auto[TlIntgErrNone]	full_word	auto[0]	73370653	1			T1	100842		T2	7374		T3	39631
auto[TlIntgErrNone]	full_word	auto[1]	115954100	1			T1	89930		T2	2767		T3	19667
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T126	2		T128	3		T171	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T126	2		T127	2		T128	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T126	1		T173	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T171	1		T170	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T126	5		T127	2		T128	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T126	5		T127	2		T128	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T175	1		T174	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T175	1		T177	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T126	2		T128	1		T171	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T126	3		T127	4		T128	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T171	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T170	2		T178	1		T176	1