Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1130741	0	0
entropy_period_rd_A	2147483647	2082	0	0
intr_enable_rd_A	2147483647	2737	0	0
prefix_0_rd_A	2147483647	1939	0	0
prefix_10_rd_A	2147483647	2071	0	0
prefix_1_rd_A	2147483647	1893	0	0
prefix_2_rd_A	2147483647	1990	0	0
prefix_3_rd_A	2147483647	2079	0	0
prefix_4_rd_A	2147483647	1945	0	0
prefix_5_rd_A	2147483647	1902	0	0
prefix_6_rd_A	2147483647	1891	0	0
prefix_7_rd_A	2147483647	1992	0	0
prefix_8_rd_A	2147483647	1678	0	0
prefix_9_rd_A	2147483647	1967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1130741	0	0
T12	350646	0	0	0
T15	906548	88183	0	0
T17	746187	0	0	0
T19	456608	0	0	0
T22	0	35559	0	0
T24	0	14422	0	0
T39	533131	0	0	0
T40	224135	0	0	0
T55	0	64444	0	0
T58	154398	0	0	0
T60	0	107200	0	0
T67	201114	0	0	0
T78	0	29118	0	0
T114	1843	0	0	0
T115	1719	0	0	0
T132	0	39212	0	0
T133	0	26149	0	0
T134	0	21662	0	0
T135	0	59920	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T78	402981	98	0	0
T79	0	174	0	0
T80	0	100	0	0
T86	0	24	0	0
T88	0	18	0	0
T101	0	26	0	0
T127	0	63	0	0
T148	0	11	0	0
T149	0	15	0	0
T150	0	23	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2737	0	0
T78	402981	84	0	0
T79	0	171	0	0
T80	0	92	0	0
T86	0	28	0	0
T88	0	16	0	0
T101	0	15	0	0
T127	0	101	0	0
T148	0	21	0	0
T149	0	7	0	0
T150	0	18	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1939	0	0
T78	402981	97	0	0
T79	0	230	0	0
T80	0	86	0	0
T86	0	26	0	0
T88	0	20	0	0
T101	0	25	0	0
T127	0	46	0	0
T148	0	5	0	0
T149	0	16	0	0
T150	0	6	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2071	0	0
T78	402981	97	0	0
T79	0	246	0	0
T80	0	136	0	0
T86	0	18	0	0
T88	0	15	0	0
T101	0	26	0	0
T127	0	33	0	0
T148	0	9	0	0
T149	0	11	0	0
T150	0	9	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1893	0	0
T78	402981	76	0	0
T79	0	239	0	0
T80	0	118	0	0
T86	0	21	0	0
T88	0	16	0	0
T101	0	22	0	0
T127	0	33	0	0
T148	0	11	0	0
T149	0	17	0	0
T150	0	7	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T78	402981	120	0	0
T79	0	203	0	0
T80	0	88	0	0
T86	0	4	0	0
T88	0	7	0	0
T101	0	21	0	0
T127	0	27	0	0
T148	0	5	0	0
T149	0	17	0	0
T150	0	4	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2079	0	0
T78	402981	109	0	0
T79	0	234	0	0
T80	0	136	0	0
T86	0	17	0	0
T88	0	25	0	0
T101	0	18	0	0
T127	0	40	0	0
T148	0	3	0	0
T149	0	17	0	0
T150	0	9	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1945	0	0
T78	402981	90	0	0
T79	0	214	0	0
T80	0	97	0	0
T86	0	12	0	0
T88	0	15	0	0
T101	0	24	0	0
T127	0	50	0	0
T148	0	14	0	0
T149	0	17	0	0
T150	0	14	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1902	0	0
T78	402981	128	0	0
T79	0	242	0	0
T80	0	99	0	0
T86	0	17	0	0
T88	0	11	0	0
T101	0	28	0	0
T127	0	52	0	0
T148	0	18	0	0
T149	0	16	0	0
T150	0	2	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1891	0	0
T78	402981	73	0	0
T79	0	215	0	0
T80	0	126	0	0
T86	0	16	0	0
T87	0	28	0	0
T88	0	20	0	0
T101	0	29	0	0
T127	0	56	0	0
T148	0	13	0	0
T149	0	16	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1992	0	0
T78	402981	89	0	0
T79	0	218	0	0
T80	0	98	0	0
T86	0	8	0	0
T88	0	20	0	0
T101	0	23	0	0
T127	0	42	0	0
T148	0	7	0	0
T149	0	22	0	0
T150	0	8	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T78	402981	106	0	0
T79	0	123	0	0
T80	0	101	0	0
T86	0	16	0	0
T88	0	13	0	0
T101	0	22	0	0
T127	0	30	0	0
T148	0	13	0	0
T149	0	18	0	0
T150	0	6	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967	0	0
T78	402981	92	0	0
T79	0	215	0	0
T80	0	109	0	0
T86	0	14	0	0
T88	0	14	0	0
T101	0	31	0	0
T127	0	42	0	0
T148	0	14	0	0
T149	0	6	0	0
T150	0	3	0	0
T151	11592	0	0	0
T152	233542	0	0	0
T153	198770	0	0	0
T154	502570	0	0	0
T155	330351	0	0	0
T156	423557	0	0	0
T157	111944	0	0	0
T158	970559	0	0	0
T159	146126	0	0	0