Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263869058

1

T1

4966

T2

9

T3

391147

full_word

185319487

1

T1

22198

T2

134

T3

250237

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	449188285	1			T1	27164		T2	143		T3	641384
auto[TlIntgErrCmd]	85	1			T136	2		T137	4		T138	2
auto[TlIntgErrData]	89	1			T136	4		T137	1		T138	5
auto[TlIntgErrBoth]	86	1			T136	4		T137	5		T138	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230775186

1

T1

16761

T2

58

T3

323065

auto[1]

218413359

1

T1

10403

T2

85

T3

318319

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159364579	1			T1	2826		T2	3		T3	236416
auto[TlIntgErrNone]	partial	auto[1]	104504239	1			T1	2140		T2	6		T3	154731
auto[TlIntgErrNone]	full_word	auto[0]	71410480	1			T1	13935		T2	55		T3	86649
auto[TlIntgErrNone]	full_word	auto[1]	113908987	1			T1	8263		T2	79		T3	163588
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T136	1		T137	2		T138	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T137	1		T138	1		T196	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T136	1		T137	1		T196	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T136	3		T138	1		T196	3
auto[TlIntgErrData]	partial	auto[1]	36	1			T136	1		T137	1		T138	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T197	1		T198	1		T199	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T138	1		T200	1		T201	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T136	4		T137	2		T138	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T137	3		T196	4		T197	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T196	1		T200	1		T201	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T199	1		T202	1		T203	1