Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1036245	0	0
entropy_period_rd_A	2147483647	1732	0	0
intr_enable_rd_A	2147483647	2117	0	0
prefix_0_rd_A	2147483647	1311	0	0
prefix_10_rd_A	2147483647	1260	0	0
prefix_1_rd_A	2147483647	1318	0	0
prefix_2_rd_A	2147483647	1394	0	0
prefix_3_rd_A	2147483647	1333	0	0
prefix_4_rd_A	2147483647	1238	0	0
prefix_5_rd_A	2147483647	1427	0	0
prefix_6_rd_A	2147483647	1250	0	0
prefix_7_rd_A	2147483647	1379	0	0
prefix_8_rd_A	2147483647	1360	0	0
prefix_9_rd_A	2147483647	1304	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1036245	0	0
T23	640176	78418	0	0
T25	0	19648	0	0
T57	0	30485	0	0
T58	0	46163	0	0
T80	0	29155	0	0
T142	0	98160	0	0
T143	0	23322	0	0
T144	0	130697	0	0
T145	0	63185	0	0
T146	0	5945	0	0
T147	713286	0	0	0
T148	305154	0	0	0
T149	1079	0	0	0
T150	689228	0	0	0
T151	232122	0	0	0
T152	649010	0	0	0
T153	260492	0	0	0
T154	3722	0	0	0
T155	133402	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1732	0	0
T58	518608	137	0	0
T80	0	110	0	0
T81	0	79	0	0
T94	0	48	0	0
T136	0	76	0	0
T137	0	38	0	0
T167	0	7	0	0
T168	0	10	0	0
T169	0	2	0	0
T170	0	3	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T58	518608	123	0	0
T80	0	93	0	0
T81	0	62	0	0
T94	0	34	0	0
T136	0	102	0	0
T137	0	47	0	0
T140	0	20	0	0
T141	0	10	0	0
T167	0	22	0	0
T168	0	30	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1311	0	0
T58	518608	100	0	0
T80	0	76	0	0
T81	0	81	0	0
T94	0	23	0	0
T136	0	40	0	0
T137	0	16	0	0
T167	0	12	0	0
T168	0	17	0	0
T169	0	2	0	0
T170	0	7	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1260	0	0
T58	518608	74	0	0
T80	0	84	0	0
T81	0	84	0	0
T94	0	19	0	0
T136	0	52	0	0
T137	0	18	0	0
T167	0	5	0	0
T168	0	4	0	0
T169	0	2	0	0
T170	0	8	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1318	0	0
T58	518608	132	0	0
T80	0	90	0	0
T81	0	78	0	0
T94	0	13	0	0
T136	0	45	0	0
T137	0	31	0	0
T167	0	13	0	0
T168	0	3	0	0
T169	0	1	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0
T180	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1394	0	0
T58	518608	113	0	0
T80	0	79	0	0
T81	0	54	0	0
T94	0	30	0	0
T136	0	41	0	0
T137	0	25	0	0
T167	0	9	0	0
T168	0	4	0	0
T169	0	5	0	0
T170	0	2	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1333	0	0
T58	518608	168	0	0
T80	0	82	0	0
T81	0	72	0	0
T94	0	33	0	0
T136	0	26	0	0
T137	0	19	0	0
T167	0	10	0	0
T168	0	9	0	0
T170	0	3	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0
T181	0	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1238	0	0
T58	518608	83	0	0
T80	0	80	0	0
T81	0	61	0	0
T94	0	21	0	0
T136	0	49	0	0
T137	0	12	0	0
T167	0	8	0	0
T168	0	7	0	0
T169	0	5	0	0
T170	0	2	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1427	0	0
T58	518608	136	0	0
T80	0	117	0	0
T81	0	87	0	0
T94	0	18	0	0
T136	0	35	0	0
T137	0	31	0	0
T167	0	8	0	0
T168	0	8	0	0
T169	0	3	0	0
T170	0	9	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1250	0	0
T58	518608	77	0	0
T80	0	49	0	0
T81	0	66	0	0
T94	0	38	0	0
T136	0	42	0	0
T137	0	6	0	0
T167	0	3	0	0
T168	0	5	0	0
T169	0	7	0	0
T170	0	6	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1379	0	0
T58	518608	155	0	0
T80	0	94	0	0
T81	0	84	0	0
T94	0	29	0	0
T136	0	46	0	0
T137	0	36	0	0
T167	0	12	0	0
T168	0	8	0	0
T169	0	2	0	0
T170	0	7	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1360	0	0
T58	518608	64	0	0
T80	0	75	0	0
T81	0	72	0	0
T94	0	34	0	0
T136	0	54	0	0
T137	0	31	0	0
T167	0	11	0	0
T168	0	10	0	0
T169	0	4	0	0
T170	0	8	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1304	0	0
T58	518608	129	0	0
T80	0	69	0	0
T81	0	51	0	0
T94	0	17	0	0
T136	0	36	0	0
T137	0	24	0	0
T167	0	13	0	0
T168	0	9	0	0
T169	0	4	0	0
T170	0	6	0	0
T171	730403	0	0	0
T172	638590	0	0	0
T173	167480	0	0	0
T174	661274	0	0	0
T175	106489	0	0	0
T176	24560	0	0	0
T177	96791	0	0	0
T178	652494	0	0	0
T179	123419	0	0	0