Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 262904276 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 187272368 1 T1 1060 T2 1080 T3 444470



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 233288384 1 T1 759 T2 861 T3 578233
values[0x0] 104188574 1 T1 522 T2 531 T3 253086
values[0x1] 112699686 1 T1 504 T2 512 T3 276092



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 204266202 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 245910442 1 T1 1234 T2 1293 T3 591547



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1474205 1 T1 8 T2 1 T3 537
valid_sources[0x01] 1572946 1 T1 9 T2 8 T3 498
valid_sources[0x02] 1486311 1 T1 7 T2 24 T3 513
valid_sources[0x03] 1395177 1 T1 9 T2 7 T3 538
valid_sources[0x04] 1401786 1 T1 12 T2 11 T3 513
valid_sources[0x05] 1559182 1 T1 6 T2 8 T3 528
valid_sources[0x06] 1504239 1 T1 7 T2 6 T3 518
valid_sources[0x07] 1394014 1 T1 11 T2 2 T3 508
valid_sources[0x08] 1508426 1 T1 7 T2 1 T3 548
valid_sources[0x09] 1497525 1 T1 3 T2 4 T3 506
valid_sources[0x0a] 1396919 1 T1 10 T2 11 T3 520
valid_sources[0x0b] 1391205 1 T1 3 T2 4 T3 541
valid_sources[0x0c] 1399277 1 T1 1 T2 1 T3 551
valid_sources[0x0d] 1399705 1 T1 4 T3 510 T33 2561
valid_sources[0x0e] 1428712 1 T1 5 T2 11 T3 491
valid_sources[0x0f] 1393064 1 T1 8 T2 9 T3 548
valid_sources[0x10] 1393573 1 T1 4 T2 12 T3 566
valid_sources[0x11] 1391256 1 T1 10 T2 16 T3 546
valid_sources[0x12] 1412118 1 T1 5 T2 9 T3 522
valid_sources[0x13] 1442420 1 T1 10 T2 5 T3 516
valid_sources[0x14] 1396170 1 T1 9 T2 5 T3 535
valid_sources[0x15] 1400565 1 T1 2 T2 13 T3 522
valid_sources[0x16] 1396447 1 T1 4 T2 19 T3 541
valid_sources[0x17] 2341241 1 T1 7 T2 3 T3 534
valid_sources[0x18] 1399981 1 T1 7 T2 13 T3 564
valid_sources[0x19] 1406224 1 T1 6 T2 15 T3 536
valid_sources[0x1a] 3781909 1 T1 2 T2 4 T3 545
valid_sources[0x1b] 1459134 1 T1 13 T2 6 T3 532
valid_sources[0x1c] 1399079 1 T1 6 T2 4 T3 533
valid_sources[0x1d] 1418083 1 T1 9 T3 557 T33 2449
valid_sources[0x1e] 1822457 1 T1 14 T2 9 T3 510
valid_sources[0x1f] 1395823 1 T1 9 T2 1 T3 517
valid_sources[0x20] 1389533 1 T1 5 T2 2 T3 514
valid_sources[0x21] 1539235 1 T1 8 T2 5 T3 502
valid_sources[0x22] 3390676 1 T1 6 T2 7 T3 530
valid_sources[0x23] 1412391 1 T1 7 T2 8 T3 532
valid_sources[0x24] 1399138 1 T1 9 T2 2 T3 524
valid_sources[0x25] 3735068 1 T1 16 T2 5 T3 529
valid_sources[0x26] 1445544 1 T1 3 T2 8 T3 499
valid_sources[0x27] 2304342 1 T1 9 T2 13 T3 522
valid_sources[0x28] 2057617 1 T1 6 T2 2 T3 553
valid_sources[0x29] 1389075 1 T1 12 T2 3 T3 531
valid_sources[0x2a] 1395569 1 T1 4 T2 11 T3 532
valid_sources[0x2b] 1394330 1 T1 6 T2 6 T3 520
valid_sources[0x2c] 1397646 1 T1 14 T3 554 T33 2581
valid_sources[0x2d] 2204186 1 T1 3 T2 3 T3 546
valid_sources[0x2e] 1941483 1 T1 13 T2 13 T3 544
valid_sources[0x2f] 1405064 1 T1 15 T2 10 T3 584
valid_sources[0x30] 2062597 1 T1 11 T2 7 T3 524
valid_sources[0x31] 1451152 1 T1 3 T2 17 T3 488
valid_sources[0x32] 1391538 1 T1 2 T2 10 T3 565
valid_sources[0x33] 1394862 1 T1 7 T2 19 T3 516
valid_sources[0x34] 1396927 1 T1 4 T2 2 T3 537
valid_sources[0x35] 1399157 1 T1 8 T2 2 T3 560
valid_sources[0x36] 2369331 1 T1 7 T2 18 T3 972833
valid_sources[0x37] 2283288 1 T1 7 T2 9 T3 529
valid_sources[0x38] 1391436 1 T1 2 T2 8 T3 561
valid_sources[0x39] 1394470 1 T1 3 T2 3 T3 542
valid_sources[0x3a] 3355981 1 T1 8 T2 12 T3 527
valid_sources[0x3b] 1401333 1 T1 7 T2 18 T3 551
valid_sources[0x3c] 1396717 1 T1 9 T2 2 T3 520
valid_sources[0x3d] 1460132 1 T1 15 T2 27 T3 521
valid_sources[0x3e] 1391388 1 T1 11 T2 9 T3 546
valid_sources[0x3f] 1396277 1 T1 10 T2 3 T3 515
valid_sources[0x40] 1490301 1 T1 4 T2 5 T3 531
valid_sources[0x41] 1389882 1 T1 14 T3 530 T33 2624
valid_sources[0x42] 1390211 1 T1 10 T2 2 T3 540
valid_sources[0x43] 3711033 1 T1 3 T2 5 T3 547
valid_sources[0x44] 2765743 1 T1 3 T2 1 T3 512
valid_sources[0x45] 2343909 1 T1 8 T3 516 T33 2620
valid_sources[0x46] 1514474 1 T1 5 T2 9 T3 526
valid_sources[0x47] 1516215 1 T1 9 T2 1 T3 526
valid_sources[0x48] 1427173 1 T1 5 T2 3 T3 527
valid_sources[0x49] 1395805 1 T1 4 T2 3 T3 475
valid_sources[0x4a] 2318123 1 T1 3 T2 3 T3 517
valid_sources[0x4b] 1397929 1 T1 7 T2 12 T3 530
valid_sources[0x4c] 1395409 1 T1 4 T2 3 T3 516
valid_sources[0x4d] 1397785 1 T1 11 T2 16 T3 553
valid_sources[0x4e] 3342690 1 T1 13 T2 5 T3 523
valid_sources[0x4f] 2598008 1 T1 13 T2 8 T3 556
valid_sources[0x50] 2131851 1 T1 3 T2 24 T3 543
valid_sources[0x51] 1398590 1 T1 6 T2 1 T3 533
valid_sources[0x52] 1396980 1 T1 9 T2 2 T3 519
valid_sources[0x53] 2070450 1 T1 7 T2 3 T3 554
valid_sources[0x54] 1463885 1 T1 13 T2 5 T3 518
valid_sources[0x55] 1392226 1 T1 6 T2 1 T3 510
valid_sources[0x56] 1397210 1 T1 6 T2 3 T3 509
valid_sources[0x57] 1624343 1 T1 14 T2 6 T3 528
valid_sources[0x58] 1862088 1 T1 4 T2 8 T3 527
valid_sources[0x59] 2303164 1 T1 6 T2 6 T3 520
valid_sources[0x5a] 1396628 1 T1 8 T2 3 T3 584
valid_sources[0x5b] 1396634 1 T1 2 T2 15 T3 519
valid_sources[0x5c] 1394712 1 T1 2 T2 12 T3 500
valid_sources[0x5d] 1395155 1 T1 10 T2 12 T3 567
valid_sources[0x5e] 1431292 1 T1 16 T2 13 T3 528
valid_sources[0x5f] 2895548 1 T1 2 T2 11 T3 545
valid_sources[0x60] 3739196 1 T1 9 T2 7 T3 529
valid_sources[0x61] 1398434 1 T1 5 T2 4 T3 530
valid_sources[0x62] 1545537 1 T1 7 T2 7 T3 548
valid_sources[0x63] 1700391 1 T1 10 T2 13 T3 491
valid_sources[0x64] 3734626 1 T1 8 T2 4 T3 518
valid_sources[0x65] 1396417 1 T1 5 T2 3 T3 505
valid_sources[0x66] 1389142 1 T1 16 T2 10 T3 527
valid_sources[0x67] 1616142 1 T1 12 T2 19 T3 509
valid_sources[0x68] 1408108 1 T1 5 T2 3 T3 511
valid_sources[0x69] 1396200 1 T1 10 T2 9 T3 512
valid_sources[0x6a] 1401436 1 T1 9 T2 1 T3 517
valid_sources[0x6b] 1498171 1 T1 4 T2 12 T3 540
valid_sources[0x6c] 1401312 1 T1 12 T2 4 T3 545
valid_sources[0x6d] 1453794 1 T1 4 T2 8 T3 536
valid_sources[0x6e] 1397144 1 T1 5 T2 2 T3 563
valid_sources[0x6f] 1398642 1 T1 12 T2 9 T3 490
valid_sources[0x70] 2054823 1 T1 6 T2 3 T3 517
valid_sources[0x71] 2219963 1 T1 3 T2 3 T3 520
valid_sources[0x72] 1397418 1 T1 4 T2 3 T3 553
valid_sources[0x73] 1405636 1 T1 9 T2 4 T3 475
valid_sources[0x74] 1856039 1 T1 4 T2 4 T3 564
valid_sources[0x75] 1398262 1 T1 8 T2 7 T3 501
valid_sources[0x76] 4411972 1 T1 7 T2 12 T3 529
valid_sources[0x77] 1393114 1 T1 1 T2 1 T3 540
valid_sources[0x78] 1394075 1 T1 7 T2 3 T3 531
valid_sources[0x79] 2137001 1 T1 3 T2 10 T3 524
valid_sources[0x7a] 1487440 1 T1 12 T2 7 T3 569
valid_sources[0x7b] 1537362 1 T1 16 T2 3 T3 526
valid_sources[0x7c] 1856398 1 T1 8 T2 11 T3 522
valid_sources[0x7d] 1395925 1 T1 10 T2 8 T3 556
valid_sources[0x7e] 1394976 1 T1 3 T2 10 T3 529
valid_sources[0x7f] 1390440 1 T1 13 T2 8 T3 492
valid_sources[0x80] 1395296 1 T1 4 T2 4 T3 564



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 72497071 1 T1 356 T2 343 T3 179436
values[0x0] all_enables biggest_size 61655554 1 T1 374 T2 395 T3 143651
values[0x1] all_enables biggest_size 53119743 1 T1 330 T2 342 T3 121383

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%