Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

266291818

1

T1

725

T2

824

T3

662941

full_word

187484440

1

T1

1060

T2

1080

T3

444470

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	453775978	1			T1	1785		T2	1904		T3	110741
auto[TlIntgErrCmd]	87	1			T117	6		T118	9		T119	6
auto[TlIntgErrData]	101	1			T117	7		T118	5		T119	2
auto[TlIntgErrBoth]	92	1			T117	7		T118	6		T119	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233945870

1

T1

759

T2

861

T3

578233

auto[1]

219830388

1

T1

1026

T2

1043

T3

529178

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161395667	1			T1	403		T2	518		T3	398797
auto[TlIntgErrNone]	partial	auto[1]	104895896	1			T1	322		T2	306		T3	264144
auto[TlIntgErrNone]	full_word	auto[0]	72550058	1			T1	356		T2	343		T3	179436
auto[TlIntgErrNone]	full_word	auto[1]	114934357	1			T1	704		T2	737		T3	265034
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T117	4		T118	3		T119	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T117	2		T118	6		T119	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T180	1		T181	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T182	1		T180	2		-	-
auto[TlIntgErrData]	partial	auto[0]	57	1			T117	5		T155	6		T183	6
auto[TlIntgErrData]	partial	auto[1]	35	1			T117	1		T118	4		T119	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T118	1		T184	2		T185	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T117	1		T186	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T117	2		T118	1		T155	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T117	2		T118	5		T119	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T117	2		T155	1		T187	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T117	1		T155	1		T181	1