Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	789458	0	0
entropy_period_rd_A	2147483647	2122	0	0
intr_enable_rd_A	2147483647	3239	0	0
prefix_0_rd_A	2147483647	2550	0	0
prefix_10_rd_A	2147483647	2474	0	0
prefix_1_rd_A	2147483647	2475	0	0
prefix_2_rd_A	2147483647	2440	0	0
prefix_3_rd_A	2147483647	2536	0	0
prefix_4_rd_A	2147483647	2498	0	0
prefix_5_rd_A	2147483647	2340	0	0
prefix_6_rd_A	2147483647	2628	0	0
prefix_7_rd_A	2147483647	2448	0	0
prefix_8_rd_A	2147483647	2309	0	0
prefix_9_rd_A	2147483647	2502	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	789458	0	0
T26	474711	66195	0	0
T57	0	23993	0	0
T58	0	1155	0	0
T79	0	49991	0	0
T113	53517	0	0	0
T123	0	98297	0	0
T124	0	104290	0	0
T125	0	49428	0	0
T126	0	25890	0	0
T127	0	38671	0	0
T128	0	50427	0	0
T129	589666	0	0	0
T130	154094	0	0	0
T131	223922	0	0	0
T132	72921	0	0	0
T133	773056	0	0	0
T134	706332	0	0	0
T135	214407	0	0	0
T136	198991	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2122	0	0
T79	625548	102	0	0
T91	0	55	0	0
T92	0	4	0	0
T127	359782	0	0	0
T150	0	1	0	0
T151	0	7	0	0
T152	0	4	0	0
T153	0	9	0	0
T154	0	12	0	0
T155	0	105	0	0
T156	0	15	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3239	0	0
T79	625548	133	0	0
T91	0	37	0	0
T120	0	24	0	0
T122	0	11	0	0
T127	359782	0	0	0
T150	0	5	0	0
T151	0	6	0	0
T152	0	11	0	0
T153	0	12	0	0
T154	0	12	0	0
T155	0	147	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T79	625548	156	0	0
T91	0	35	0	0
T92	0	13	0	0
T127	359782	0	0	0
T150	0	5	0	0
T151	0	9	0	0
T152	0	56	0	0
T153	0	4	0	0
T154	0	1	0	0
T155	0	61	0	0
T156	0	3	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T79	625548	150	0	0
T91	0	52	0	0
T127	359782	0	0	0
T150	0	4	0	0
T151	0	18	0	0
T152	0	55	0	0
T153	0	12	0	0
T154	0	6	0	0
T155	0	83	0	0
T156	0	8	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T165	0	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2475	0	0
T79	625548	135	0	0
T91	0	29	0	0
T92	0	5	0	0
T127	359782	0	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	10	0	0
T153	0	10	0	0
T155	0	93	0	0
T156	0	2	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T166	0	250	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T79	625548	125	0	0
T91	0	21	0	0
T92	0	2	0	0
T127	359782	0	0	0
T151	0	8	0	0
T152	0	26	0	0
T153	0	14	0	0
T154	0	21	0	0
T155	0	63	0	0
T156	0	12	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T165	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2536	0	0
T79	625548	162	0	0
T91	0	27	0	0
T92	0	2	0	0
T127	359782	0	0	0
T151	0	7	0	0
T152	0	8	0	0
T153	0	10	0	0
T154	0	8	0	0
T155	0	71	0	0
T156	0	11	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T166	0	245	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2498	0	0
T79	625548	108	0	0
T91	0	34	0	0
T92	0	3	0	0
T127	359782	0	0	0
T150	0	10	0	0
T151	0	10	0	0
T152	0	7	0	0
T153	0	1	0	0
T154	0	10	0	0
T155	0	93	0	0
T156	0	15	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2340	0	0
T79	625548	146	0	0
T91	0	37	0	0
T92	0	8	0	0
T127	359782	0	0	0
T150	0	5	0	0
T151	0	8	0	0
T153	0	6	0	0
T154	0	21	0	0
T155	0	73	0	0
T156	0	9	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T165	0	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2628	0	0
T79	625548	89	0	0
T91	0	36	0	0
T92	0	7	0	0
T127	359782	0	0	0
T150	0	1	0	0
T151	0	12	0	0
T152	0	56	0	0
T153	0	16	0	0
T155	0	116	0	0
T156	0	1	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T165	0	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2448	0	0
T79	625548	107	0	0
T91	0	25	0	0
T92	0	8	0	0
T127	359782	0	0	0
T150	0	6	0	0
T151	0	8	0	0
T152	0	23	0	0
T153	0	4	0	0
T154	0	13	0	0
T155	0	82	0	0
T156	0	7	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2309	0	0
T79	625548	114	0	0
T91	0	43	0	0
T127	359782	0	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	51	0	0
T153	0	8	0	0
T155	0	70	0	0
T156	0	9	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T165	0	5	0	0
T167	0	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2502	0	0
T79	625548	131	0	0
T91	0	28	0	0
T127	359782	0	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	4	0	0
T153	0	5	0	0
T154	0	7	0	0
T155	0	93	0	0
T157	621025	0	0	0
T158	21770	0	0	0
T159	407069	0	0	0
T160	60040	0	0	0
T161	3693	0	0	0
T162	862491	0	0	0
T163	327446	0	0	0
T164	492587	0	0	0
T165	0	5	0	0
T167	0	1	0	0