Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177735 |
1 |
|
|
T7 |
790 |
|
T8 |
603 |
|
T33 |
415 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
94233 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60809 |
1 |
|
|
T7 |
19 |
|
T8 |
592 |
|
T33 |
407 |
seven_bytes |
3246 |
1 |
|
|
T7 |
28 |
|
T15 |
57 |
|
T67 |
79 |
six_bytes |
3211 |
1 |
|
|
T7 |
23 |
|
T15 |
46 |
|
T67 |
83 |
five_bytes |
3280 |
1 |
|
|
T7 |
26 |
|
T15 |
51 |
|
T67 |
82 |
four_bytes |
3258 |
1 |
|
|
T7 |
21 |
|
T15 |
52 |
|
T67 |
83 |
three_bytes |
3309 |
1 |
|
|
T7 |
20 |
|
T15 |
46 |
|
T67 |
110 |
two_bytes |
3195 |
1 |
|
|
T7 |
22 |
|
T15 |
50 |
|
T67 |
87 |
one_byte |
3194 |
1 |
|
|
T7 |
28 |
|
T15 |
49 |
|
T67 |
101 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174377 |
1 |
|
|
T7 |
778 |
|
T8 |
581 |
|
T33 |
399 |
auto[1] |
3358 |
1 |
|
|
T7 |
12 |
|
T8 |
22 |
|
T33 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177735 |
1 |
|
|
T7 |
790 |
|
T8 |
603 |
|
T33 |
415 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177727 |
1 |
|
|
T7 |
790 |
|
T8 |
603 |
|
T33 |
415 |
auto[1] |
8 |
1 |
|
|
T178 |
1 |
|
T179 |
1 |
|
T180 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1135 |
1 |
|
|
T7 |
2 |
|
T8 |
11 |
|
T33 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3358 |
1 |
|
|
T7 |
12 |
|
T8 |
22 |
|
T33 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179099 |
1 |
|
|
T3 |
5 |
|
T7 |
483 |
|
T8 |
215 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
95209 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61154 |
1 |
|
|
T3 |
4 |
|
T7 |
12 |
|
T8 |
209 |
seven_bytes |
3195 |
1 |
|
|
T7 |
11 |
|
T15 |
83 |
|
T67 |
69 |
six_bytes |
3362 |
1 |
|
|
T7 |
18 |
|
T15 |
51 |
|
T67 |
80 |
five_bytes |
3305 |
1 |
|
|
T7 |
11 |
|
T15 |
59 |
|
T67 |
85 |
four_bytes |
3175 |
1 |
|
|
T7 |
11 |
|
T15 |
58 |
|
T67 |
62 |
three_bytes |
3296 |
1 |
|
|
T7 |
10 |
|
T15 |
78 |
|
T67 |
74 |
two_bytes |
3199 |
1 |
|
|
T7 |
18 |
|
T15 |
69 |
|
T67 |
72 |
one_byte |
3204 |
1 |
|
|
T7 |
19 |
|
T15 |
64 |
|
T67 |
75 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175757 |
1 |
|
|
T3 |
3 |
|
T7 |
477 |
|
T8 |
203 |
auto[1] |
3342 |
1 |
|
|
T3 |
2 |
|
T7 |
6 |
|
T8 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179099 |
1 |
|
|
T3 |
5 |
|
T7 |
483 |
|
T8 |
215 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
179086 |
1 |
|
|
T3 |
5 |
|
T7 |
483 |
|
T8 |
215 |
auto[1] |
13 |
1 |
|
|
T17 |
1 |
|
T9 |
1 |
|
T181 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1136 |
1 |
|
|
T3 |
1 |
|
T7 |
1 |
|
T8 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3342 |
1 |
|
|
T3 |
2 |
|
T7 |
6 |
|
T8 |
12 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356084 |
1 |
|
|
T3 |
20 |
|
T7 |
2355 |
|
T8 |
1896 |
auto[1] |
556 |
1 |
|
|
T6 |
15 |
|
T9 |
89 |
|
T10 |
75 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
190505 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
120437 |
1 |
|
|
T3 |
19 |
|
T7 |
68 |
|
T8 |
1374 |
seven_bytes |
6630 |
1 |
|
|
T7 |
68 |
|
T8 |
18 |
|
T15 |
80 |
six_bytes |
6627 |
1 |
|
|
T7 |
54 |
|
T8 |
15 |
|
T15 |
70 |
five_bytes |
6583 |
1 |
|
|
T7 |
64 |
|
T8 |
11 |
|
T15 |
80 |
four_bytes |
6559 |
1 |
|
|
T7 |
60 |
|
T8 |
17 |
|
T15 |
69 |
three_bytes |
6482 |
1 |
|
|
T7 |
64 |
|
T8 |
8 |
|
T15 |
78 |
two_bytes |
6375 |
1 |
|
|
T7 |
71 |
|
T8 |
17 |
|
T15 |
64 |
one_byte |
6442 |
1 |
|
|
T7 |
67 |
|
T8 |
12 |
|
T15 |
73 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
350018 |
1 |
|
|
T3 |
18 |
|
T7 |
2325 |
|
T8 |
1854 |
auto[1] |
6622 |
1 |
|
|
T3 |
2 |
|
T7 |
30 |
|
T8 |
42 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356640 |
1 |
|
|
T3 |
20 |
|
T7 |
2355 |
|
T8 |
1896 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356608 |
1 |
|
|
T3 |
20 |
|
T7 |
2355 |
|
T8 |
1896 |
auto[1] |
32 |
1 |
|
|
T99 |
1 |
|
T9 |
1 |
|
T10 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2245 |
1 |
|
|
T3 |
1 |
|
T7 |
6 |
|
T8 |
19 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6622 |
1 |
|
|
T3 |
2 |
|
T7 |
30 |
|
T8 |
42 |