Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 257359840 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 183761711 1 T1 249932 T2 324184 T3 118538



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 228251216 1 T1 330307 T2 430501 T3 133604
values[0x0] 102285276 1 T1 155633 T2 205057 T3 32129
values[0x1] 110585059 1 T1 169883 T2 222708 T3 34660



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 199976793 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 241144758 1 T1 339306 T2 442451 T3 137908



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1334369 1 T2 3349 T3 814 T4 1
valid_sources[0x01] 1979784 1 T2 3297 T3 810 T4 3
valid_sources[0x02] 1329466 1 T2 3292 T3 796 T29 109
valid_sources[0x03] 1342156 1 T2 3398 T3 787 T29 94
valid_sources[0x04] 1334418 1 T2 3319 T3 808 T4 1
valid_sources[0x05] 1789791 1 T2 3446 T3 763 T29 126
valid_sources[0x06] 1333531 1 T2 3415 T3 736 T4 3
valid_sources[0x07] 1329793 1 T2 3342 T3 835 T4 1
valid_sources[0x08] 1330186 1 T2 3248 T3 769 T4 2
valid_sources[0x09] 1777872 1 T2 3306 T3 780 T4 4
valid_sources[0x0a] 1332822 1 T2 3339 T3 801 T4 2
valid_sources[0x0b] 1336242 1 T2 3368 T3 793 T4 1
valid_sources[0x0c] 1332327 1 T2 3455 T3 765 T4 3
valid_sources[0x0d] 3783375 1 T2 3212 T3 782 T4 2
valid_sources[0x0e] 2241427 1 T2 3352 T3 739 T4 1
valid_sources[0x0f] 1324030 1 T2 3299 T3 777 T4 1
valid_sources[0x10] 1325582 1 T2 3309 T3 782 T4 1
valid_sources[0x11] 1778481 1 T2 3405 T3 856 T4 1
valid_sources[0x12] 1414841 1 T2 3445 T3 770 T4 2
valid_sources[0x13] 1330248 1 T2 3232 T3 679 T4 3
valid_sources[0x14] 1327390 1 T2 3370 T3 772 T29 103
valid_sources[0x15] 1327964 1 T2 3264 T3 809 T4 1
valid_sources[0x16] 1332534 1 T2 3348 T3 771 T4 3
valid_sources[0x17] 1339284 1 T2 3295 T3 765 T4 1
valid_sources[0x18] 1519253 1 T2 3354 T3 732 T29 40
valid_sources[0x19] 3426134 1 T2 3423 T3 825 T4 5
valid_sources[0x1a] 2365466 1 T2 3344 T3 747 T29 36
valid_sources[0x1b] 1331222 1 T2 3287 T3 781 T4 1
valid_sources[0x1c] 1332854 1 T2 3424 T3 845 T4 2
valid_sources[0x1d] 1330580 1 T2 3216 T3 743 T4 1
valid_sources[0x1e] 1463904 1 T2 3277 T3 771 T4 3
valid_sources[0x1f] 1329556 1 T2 3323 T3 772 T4 1
valid_sources[0x20] 1329589 1 T2 3321 T3 815 T29 88
valid_sources[0x21] 2205788 1 T2 3370 T3 778 T4 1
valid_sources[0x22] 1333240 1 T2 3307 T3 755 T4 1
valid_sources[0x23] 4552331 1 T2 3536 T3 799 T4 3
valid_sources[0x24] 1476810 1 T2 3360 T3 787 T29 124
valid_sources[0x25] 1336280 1 T2 3493 T3 791 T4 1
valid_sources[0x26] 2560268 1 T2 3306 T3 845 T4 3
valid_sources[0x27] 1332877 1 T2 3405 T3 762 T4 1
valid_sources[0x28] 1789987 1 T2 3330 T3 816 T29 104
valid_sources[0x29] 3459089 1 T2 3383 T3 847 T29 82
valid_sources[0x2a] 1413824 1 T2 3329 T3 775 T29 83
valid_sources[0x2b] 1336334 1 T2 3428 T3 799 T4 1
valid_sources[0x2c] 1329384 1 T2 3402 T3 847 T4 1
valid_sources[0x2d] 1334691 1 T2 3480 T3 745 T4 1
valid_sources[0x2e] 1337581 1 T2 3337 T3 794 T4 1
valid_sources[0x2f] 1365695 1 T2 3335 T3 685 T29 95
valid_sources[0x30] 1331451 1 T2 3333 T3 807 T4 1
valid_sources[0x31] 1330399 1 T2 3367 T3 792 T29 51
valid_sources[0x32] 1494981 1 T2 3432 T3 774 T4 2
valid_sources[0x33] 1325275 1 T2 3366 T3 866 T29 82
valid_sources[0x34] 1338761 1 T2 3308 T3 779 T4 3
valid_sources[0x35] 2178046 1 T2 3256 T3 814 T4 2
valid_sources[0x36] 3302860 1 T2 3365 T3 808 T4 4
valid_sources[0x37] 1335325 1 T2 3279 T3 775 T4 3
valid_sources[0x38] 1392250 1 T2 3409 T3 805 T4 3
valid_sources[0x39] 3654351 1 T2 3329 T3 834 T29 92
valid_sources[0x3a] 1445592 1 T2 3318 T3 771 T4 1
valid_sources[0x3b] 1541333 1 T2 3460 T3 775 T29 38
valid_sources[0x3c] 3414877 1 T2 3359 T3 795 T4 2
valid_sources[0x3d] 5951872 1 T2 3383 T3 867 T4 1
valid_sources[0x3e] 1338292 1 T2 3312 T3 776 T4 2
valid_sources[0x3f] 1327572 1 T2 3401 T3 779 T29 81
valid_sources[0x40] 5625144 1 T2 3308 T3 793 T4 2
valid_sources[0x41] 1993003 1 T2 3340 T3 795 T4 1
valid_sources[0x42] 2321857 1 T2 3348 T3 825 T4 3
valid_sources[0x43] 3684433 1 T2 3343 T3 743 T4 7
valid_sources[0x44] 1330095 1 T2 3273 T3 748 T4 2
valid_sources[0x45] 1328627 1 T2 3363 T3 743 T4 2
valid_sources[0x46] 1329175 1 T2 3453 T3 734 T29 88
valid_sources[0x47] 1352783 1 T2 3438 T3 734 T4 1
valid_sources[0x48] 2326840 1 T2 3368 T3 755 T4 5
valid_sources[0x49] 1327019 1 T2 3350 T3 845 T4 1
valid_sources[0x4a] 3255536 1 T2 3313 T3 754 T4 1
valid_sources[0x4b] 1333321 1 T2 3420 T3 821 T4 2
valid_sources[0x4c] 1407149 1 T2 3390 T3 859 T4 1
valid_sources[0x4d] 1350732 1 T2 3409 T3 750 T29 105
valid_sources[0x4e] 1357342 1 T2 3264 T3 830 T4 1
valid_sources[0x4f] 1332398 1 T2 3272 T3 797 T4 1
valid_sources[0x50] 1802191 1 T2 3368 T3 778 T4 2
valid_sources[0x51] 1327368 1 T2 3415 T3 745 T4 2
valid_sources[0x52] 1345341 1 T2 3355 T3 730 T29 32
valid_sources[0x53] 1325311 1 T2 3294 T3 790 T4 2
valid_sources[0x54] 5328657 1 T2 3322 T3 780 T4 1
valid_sources[0x55] 1965682 1 T2 3231 T3 709 T4 4
valid_sources[0x56] 1331931 1 T2 3175 T3 758 T4 3
valid_sources[0x57] 2191196 1 T2 3429 T3 799 T4 1
valid_sources[0x58] 1990773 1 T2 3213 T3 743 T4 1
valid_sources[0x59] 1323281 1 T2 3411 T3 752 T29 65
valid_sources[0x5a] 1332743 1 T2 3340 T3 787 T4 2
valid_sources[0x5b] 1333038 1 T2 3370 T3 767 T29 75
valid_sources[0x5c] 4985801 1 T2 3334 T3 772 T4 2
valid_sources[0x5d] 1936817 1 T2 3394 T3 814 T4 2
valid_sources[0x5e] 1338653 1 T2 3387 T3 847 T4 2
valid_sources[0x5f] 1333346 1 T2 3286 T3 719 T4 1
valid_sources[0x60] 1328195 1 T2 3335 T3 771 T4 1
valid_sources[0x61] 1329899 1 T2 3388 T3 782 T29 82
valid_sources[0x62] 1330635 1 T2 3282 T3 792 T4 2
valid_sources[0x63] 1592454 1 T2 3371 T3 780 T4 2
valid_sources[0x64] 1327074 1 T2 3387 T3 750 T29 81
valid_sources[0x65] 3257113 1 T2 3371 T3 761 T4 1
valid_sources[0x66] 1376871 1 T2 3394 T3 774 T4 1
valid_sources[0x67] 1326044 1 T2 3441 T3 836 T4 2
valid_sources[0x68] 1333222 1 T2 3313 T3 746 T4 2
valid_sources[0x69] 1332451 1 T2 3293 T3 745 T4 2
valid_sources[0x6a] 1337745 1 T2 3396 T3 845 T4 1
valid_sources[0x6b] 1324333 1 T2 3339 T3 754 T4 5
valid_sources[0x6c] 1330176 1 T2 3265 T3 716 T4 3
valid_sources[0x6d] 2215130 1 T2 3344 T3 802 T4 1
valid_sources[0x6e] 1786179 1 T2 3367 T3 850 T4 1
valid_sources[0x6f] 1364889 1 T2 3268 T3 773 T4 1
valid_sources[0x70] 1326545 1 T2 3263 T3 766 T29 25
valid_sources[0x71] 1352080 1 T2 3391 T3 825 T29 107
valid_sources[0x72] 1802100 1 T2 3333 T3 814 T4 1
valid_sources[0x73] 3642125 1 T2 3353 T3 784 T4 3
valid_sources[0x74] 1693333 1 T2 3384 T3 752 T4 3
valid_sources[0x75] 3290864 1 T2 3367 T3 762 T4 2
valid_sources[0x76] 1333958 1 T2 3278 T3 759 T4 2
valid_sources[0x77] 1980155 1 T2 3415 T3 789 T4 2
valid_sources[0x78] 3329121 1 T2 3340 T3 800 T29 46
valid_sources[0x79] 1333502 1 T2 3303 T3 808 T4 3
valid_sources[0x7a] 1326486 1 T2 3359 T3 783 T4 1
valid_sources[0x7b] 1328320 1 T2 3422 T3 800 T4 3
valid_sources[0x7c] 1333944 1 T2 3353 T3 831 T29 84
valid_sources[0x7d] 1332340 1 T2 3422 T3 761 T4 3
valid_sources[0x7e] 1993819 1 T1 655823 T2 3332 T3 775
valid_sources[0x7f] 1327015 1 T2 3370 T3 740 T4 3
valid_sources[0x80] 1329296 1 T2 3301 T3 795 T4 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 70810115 1 T1 88499 T2 112522 T3 80897
values[0x0] all_enables biggest_size 60655785 1 T1 87475 T2 115137 T3 19938
values[0x1] all_enables biggest_size 52295811 1 T1 73958 T2 96525 T3 17703

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%