Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259852227

1

T1

405891

T2

534082

T3

81855

full_word

183917652

1

T1

249932

T2

324184

T3

118538

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443769579	1			T1	655823		T2	858266		T3	200393
auto[TlIntgErrCmd]	98	1			T127	11		T128	4		T129	9
auto[TlIntgErrData]	96	1			T127	6		T128	3		T129	6
auto[TlIntgErrBoth]	106	1			T127	3		T128	3		T129	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228736132

1

T1

330307

T2

430501

T3

133604

auto[1]

215033747

1

T1

325516

T2

427765

T3

66789

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157886703	1			T1	241808		T2	317979		T3	52707
auto[TlIntgErrNone]	partial	auto[1]	101965255	1			T1	164083		T2	216103		T3	29148
auto[TlIntgErrNone]	full_word	auto[0]	70849291	1			T1	88499		T2	112522		T3	80897
auto[TlIntgErrNone]	full_word	auto[1]	113068330	1			T1	161433		T2	211662		T3	37641
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T127	4		T128	1		T129	4
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T127	5		T128	1		T129	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T189	1		T190	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T127	2		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T127	2		T128	2		T129	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T127	4		T128	1		T129	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T188	1		T191	1		T192	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T183	1		T184	1		T185	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T127	2		T128	2		T129	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T127	1		T128	1		T129	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T183	2		T186	1		T188	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T183	1		T185	1		T192	1