Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	574839	0	0
entropy_period_rd_A	2147483647	1678	0	0
intr_enable_rd_A	2147483647	2198	0	0
prefix_0_rd_A	2147483647	1337	0	0
prefix_10_rd_A	2147483647	1397	0	0
prefix_1_rd_A	2147483647	1349	0	0
prefix_2_rd_A	2147483647	1392	0	0
prefix_3_rd_A	2147483647	1361	0	0
prefix_4_rd_A	2147483647	1386	0	0
prefix_5_rd_A	2147483647	1409	0	0
prefix_6_rd_A	2147483647	1372	0	0
prefix_7_rd_A	2147483647	1331	0	0
prefix_8_rd_A	2147483647	1324	0	0
prefix_9_rd_A	2147483647	1385	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	574839	0	0
T21	215048	22095	0	0
T43	611799	84380	0	0
T44	0	26167	0	0
T45	0	11843	0	0
T68	127826	0	0	0
T80	0	19661	0	0
T133	0	24973	0	0
T134	0	23152	0	0
T135	0	62490	0	0
T136	0	58305	0	0
T137	0	39594	0	0
T138	740524	0	0	0
T139	195621	0	0	0
T140	655007	0	0	0
T141	30932	0	0	0
T142	106148	0	0	0
T143	176220	0	0	0
T144	223231	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1678	0	0
T45	180598	39	0	0
T80	0	56	0	0
T81	0	67	0	0
T85	0	10	0	0
T86	0	69	0	0
T127	0	153	0	0
T155	0	43	0	0
T156	0	23	0	0
T157	0	7	0	0
T158	0	70	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2198	0	0
T45	180598	38	0	0
T80	0	22	0	0
T81	0	82	0	0
T85	0	4	0	0
T86	0	100	0	0
T127	0	182	0	0
T155	0	17	0	0
T156	0	30	0	0
T157	0	22	0	0
T158	0	156	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1337	0	0
T45	180598	24	0	0
T80	0	20	0	0
T81	0	97	0	0
T85	0	13	0	0
T86	0	61	0	0
T127	0	113	0	0
T155	0	32	0	0
T156	0	11	0	0
T157	0	3	0	0
T158	0	129	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1397	0	0
T45	180598	60	0	0
T80	0	3	0	0
T81	0	68	0	0
T85	0	18	0	0
T86	0	70	0	0
T127	0	68	0	0
T155	0	46	0	0
T156	0	18	0	0
T157	0	5	0	0
T158	0	141	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1349	0	0
T45	180598	65	0	0
T80	0	36	0	0
T81	0	86	0	0
T85	0	19	0	0
T86	0	67	0	0
T127	0	75	0	0
T155	0	32	0	0
T156	0	17	0	0
T157	0	1	0	0
T158	0	129	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1392	0	0
T45	180598	35	0	0
T80	0	32	0	0
T81	0	100	0	0
T85	0	27	0	0
T86	0	46	0	0
T127	0	75	0	0
T155	0	17	0	0
T156	0	9	0	0
T157	0	1	0	0
T158	0	104	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1361	0	0
T45	180598	54	0	0
T80	0	42	0	0
T81	0	81	0	0
T85	0	15	0	0
T86	0	51	0	0
T127	0	61	0	0
T155	0	27	0	0
T156	0	20	0	0
T157	0	6	0	0
T158	0	139	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1386	0	0
T45	180598	47	0	0
T80	0	27	0	0
T81	0	88	0	0
T85	0	13	0	0
T86	0	58	0	0
T127	0	84	0	0
T128	0	21	0	0
T155	0	45	0	0
T156	0	13	0	0
T158	0	138	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1409	0	0
T45	180598	41	0	0
T80	0	71	0	0
T81	0	74	0	0
T85	0	14	0	0
T86	0	54	0	0
T127	0	99	0	0
T155	0	34	0	0
T156	0	11	0	0
T157	0	2	0	0
T158	0	103	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T45	180598	62	0	0
T80	0	8	0	0
T81	0	50	0	0
T85	0	22	0	0
T86	0	56	0	0
T127	0	92	0	0
T155	0	23	0	0
T156	0	15	0	0
T157	0	2	0	0
T158	0	155	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1331	0	0
T45	180598	45	0	0
T80	0	42	0	0
T81	0	93	0	0
T85	0	18	0	0
T86	0	66	0	0
T127	0	64	0	0
T155	0	30	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	141	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1324	0	0
T45	180598	64	0	0
T80	0	47	0	0
T81	0	71	0	0
T85	0	17	0	0
T86	0	53	0	0
T127	0	76	0	0
T128	0	19	0	0
T155	0	33	0	0
T156	0	15	0	0
T158	0	104	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1385	0	0
T45	180598	66	0	0
T80	0	53	0	0
T81	0	70	0	0
T85	0	14	0	0
T86	0	36	0	0
T127	0	92	0	0
T155	0	40	0	0
T156	0	26	0	0
T157	0	3	0	0
T158	0	143	0	0
T159	536227	0	0	0
T160	633372	0	0	0
T161	625958	0	0	0
T162	156088	0	0	0
T163	518135	0	0	0
T164	376036	0	0	0
T165	24598	0	0	0
T166	189729	0	0	0
T167	34584	0	0	0