Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171068 |
1 |
|
|
T2 |
248 |
|
T5 |
1243 |
|
T20 |
73 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91334 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57929 |
1 |
|
|
T2 |
243 |
|
T5 |
1228 |
|
T20 |
72 |
seven_bytes |
3104 |
1 |
|
|
T19 |
67 |
|
T15 |
10 |
|
T95 |
69 |
six_bytes |
3100 |
1 |
|
|
T19 |
68 |
|
T15 |
10 |
|
T95 |
62 |
five_bytes |
3122 |
1 |
|
|
T19 |
59 |
|
T15 |
14 |
|
T95 |
57 |
four_bytes |
3252 |
1 |
|
|
T19 |
52 |
|
T15 |
16 |
|
T95 |
53 |
three_bytes |
2994 |
1 |
|
|
T19 |
57 |
|
T15 |
11 |
|
T95 |
62 |
two_bytes |
3145 |
1 |
|
|
T19 |
65 |
|
T15 |
8 |
|
T95 |
73 |
one_byte |
3088 |
1 |
|
|
T19 |
67 |
|
T15 |
13 |
|
T95 |
53 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167866 |
1 |
|
|
T2 |
238 |
|
T5 |
1213 |
|
T20 |
71 |
auto[1] |
3202 |
1 |
|
|
T2 |
10 |
|
T5 |
30 |
|
T20 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171068 |
1 |
|
|
T2 |
248 |
|
T5 |
1243 |
|
T20 |
73 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171050 |
1 |
|
|
T2 |
248 |
|
T5 |
1243 |
|
T20 |
73 |
auto[1] |
18 |
1 |
|
|
T19 |
2 |
|
T15 |
2 |
|
T97 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1062 |
1 |
|
|
T2 |
5 |
|
T5 |
15 |
|
T20 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3202 |
1 |
|
|
T2 |
10 |
|
T5 |
30 |
|
T20 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
187301 |
1 |
|
|
T2 |
315 |
|
T7 |
61 |
|
T5 |
1720 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
100775 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62511 |
1 |
|
|
T2 |
311 |
|
T7 |
60 |
|
T5 |
1693 |
seven_bytes |
3417 |
1 |
|
|
T19 |
51 |
|
T15 |
10 |
|
T95 |
69 |
six_bytes |
3417 |
1 |
|
|
T19 |
78 |
|
T15 |
9 |
|
T95 |
48 |
five_bytes |
3480 |
1 |
|
|
T19 |
69 |
|
T15 |
10 |
|
T95 |
53 |
four_bytes |
3408 |
1 |
|
|
T19 |
55 |
|
T15 |
9 |
|
T95 |
53 |
three_bytes |
3487 |
1 |
|
|
T19 |
72 |
|
T15 |
8 |
|
T95 |
50 |
two_bytes |
3371 |
1 |
|
|
T19 |
64 |
|
T15 |
19 |
|
T95 |
49 |
one_byte |
3435 |
1 |
|
|
T19 |
65 |
|
T15 |
19 |
|
T95 |
56 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
183863 |
1 |
|
|
T2 |
307 |
|
T7 |
59 |
|
T5 |
1666 |
auto[1] |
3438 |
1 |
|
|
T2 |
8 |
|
T7 |
2 |
|
T5 |
54 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
187301 |
1 |
|
|
T2 |
315 |
|
T7 |
61 |
|
T5 |
1720 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
187290 |
1 |
|
|
T2 |
315 |
|
T7 |
61 |
|
T5 |
1720 |
auto[1] |
11 |
1 |
|
|
T19 |
1 |
|
T95 |
1 |
|
T163 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1161 |
1 |
|
|
T2 |
4 |
|
T7 |
1 |
|
T5 |
27 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3438 |
1 |
|
|
T2 |
8 |
|
T7 |
2 |
|
T5 |
54 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
360874 |
1 |
|
|
T2 |
1173 |
|
T5 |
3704 |
|
T18 |
234 |
auto[1] |
281 |
1 |
|
|
T5 |
57 |
|
T8 |
25 |
|
T9 |
20 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
196590 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
118001 |
1 |
|
|
T2 |
1157 |
|
T5 |
3704 |
|
T18 |
231 |
seven_bytes |
6772 |
1 |
|
|
T19 |
177 |
|
T15 |
23 |
|
T95 |
125 |
six_bytes |
6658 |
1 |
|
|
T19 |
163 |
|
T15 |
41 |
|
T95 |
82 |
five_bytes |
6610 |
1 |
|
|
T19 |
138 |
|
T15 |
29 |
|
T95 |
99 |
four_bytes |
6699 |
1 |
|
|
T19 |
145 |
|
T15 |
40 |
|
T95 |
103 |
three_bytes |
6737 |
1 |
|
|
T19 |
156 |
|
T15 |
23 |
|
T95 |
100 |
two_bytes |
6609 |
1 |
|
|
T19 |
137 |
|
T15 |
24 |
|
T95 |
107 |
one_byte |
6479 |
1 |
|
|
T19 |
172 |
|
T15 |
22 |
|
T95 |
100 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
354455 |
1 |
|
|
T2 |
1141 |
|
T5 |
3647 |
|
T18 |
228 |
auto[1] |
6700 |
1 |
|
|
T2 |
32 |
|
T5 |
114 |
|
T18 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361155 |
1 |
|
|
T2 |
1173 |
|
T5 |
3761 |
|
T18 |
234 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
361132 |
1 |
|
|
T2 |
1172 |
|
T5 |
3761 |
|
T18 |
234 |
auto[1] |
23 |
1 |
|
|
T2 |
1 |
|
T14 |
1 |
|
T19 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2225 |
1 |
|
|
T2 |
16 |
|
T5 |
57 |
|
T18 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6700 |
1 |
|
|
T2 |
32 |
|
T5 |
114 |
|
T18 |
6 |