Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

263190830

1

T1

1119

T2

150953

T3

408006

full_word

187382411

1

T1

5521

T2

181569

T3

252097

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	450572941	1			T1	6640		T2	332522		T3	660103
auto[TlIntgErrCmd]	100	1			T113	4		T114	3		T115	8
auto[TlIntgErrData]	91	1			T113	2		T114	2		T115	3
auto[TlIntgErrBoth]	109	1			T113	4		T114	5		T115	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

231626474

1

T1

4045

T2

189305

T3

331501

auto[1]

218946767

1

T1

2595

T2

143217

T3

328602

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159249207	1			T1	641		T2	93108		T3	242722
auto[TlIntgErrNone]	partial	auto[1]	103941358	1			T1	478		T2	57845		T3	165284
auto[TlIntgErrNone]	full_word	auto[0]	72377129	1			T1	3404		T2	96197		T3	88779
auto[TlIntgErrNone]	full_word	auto[1]	115005247	1			T1	2117		T2	85372		T3	163318
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T113	2		T114	1		T115	5
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T113	2		T114	1		T115	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T164	1		T169	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T114	1		T142	1		T171	3
auto[TlIntgErrData]	partial	auto[0]	38	1			T113	1		T114	1		T142	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T113	1		T114	1		T115	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T115	1		T171	1		T119	3
auto[TlIntgErrData]	full_word	auto[1]	9	1			T115	1		T165	2		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T114	1		T115	6		T142	4
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T113	3		T114	2		T115	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T113	1		T114	1		T164	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T114	1		T164	1		T173	1