Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	318671315	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1242	1242	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	318671315	0	0
T1	77574	3305	0	0
T2	357200	191634	0	0
T3	149383	491253	0	0
T4	120206	1211	0	0
T5	364623	2298	0	0
T7	370449	25967	0	0
T10	4089	127	0	0
T30	619835	638037	0	0
T31	705115	485725	0	0
T32	138428	331739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	77574	77493	0	0
T2	357200	357112	0	0
T3	149383	149375	0	0
T4	120206	120115	0	0
T5	364623	364572	0	0
T7	370449	370352	0	0
T10	4089	3950	0	0
T30	619835	619828	0	0
T31	705115	705109	0	0
T32	138428	138418	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	77574	77493	0	0
T2	357200	357112	0	0
T3	149383	149375	0	0
T4	120206	120115	0	0
T5	364623	364572	0	0
T7	370449	370352	0	0
T10	4089	3950	0	0
T30	619835	619828	0	0
T31	705115	705109	0	0
T32	138428	138418	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	77574	77493	0	0
T2	357200	357112	0	0
T3	149383	149375	0	0
T4	120206	120115	0	0
T5	364623	364572	0	0
T7	370449	370352	0	0
T10	4089	3950	0	0
T30	619835	619828	0	0
T31	705115	705109	0	0
T32	138428	138418	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1242	1242	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	620183825	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1242	1242	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	620183825	0	0
T1	77574	3305	0	0
T2	357200	871828	0	0
T3	149383	491253	0	0
T4	120206	1211	0	0
T5	364623	2298	0	0
T7	370449	25967	0	0
T10	4089	601	0	0
T30	619835	638037	0	0
T31	705115	218519	0	0
T32	138428	331739	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	77574	77493	0	0
T2	357200	357112	0	0
T3	149383	149375	0	0
T4	120206	120115	0	0
T5	364623	364572	0	0
T7	370449	370352	0	0
T10	4089	3950	0	0
T30	619835	619828	0	0
T31	705115	705109	0	0
T32	138428	138418	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	77574	77493	0	0
T2	357200	357112	0	0
T3	149383	149375	0	0
T4	120206	120115	0	0
T5	364623	364572	0	0
T7	370449	370352	0	0
T10	4089	3950	0	0
T30	619835	619828	0	0
T31	705115	705109	0	0
T32	138428	138418	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	77574	77493	0	0
T2	357200	357112	0	0
T3	149383	149375	0	0
T4	120206	120115	0	0
T5	364623	364572	0	0
T7	370449	370352	0	0
T10	4089	3950	0	0
T30	619835	619828	0	0
T31	705115	705109	0	0
T32	138428	138418	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1242	1242	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0