Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1040998	0	0
entropy_period_rd_A	2147483647	2006	0	0
intr_enable_rd_A	2147483647	2576	0	0
prefix_0_rd_A	2147483647	1789	0	0
prefix_10_rd_A	2147483647	1975	0	0
prefix_1_rd_A	2147483647	1929	0	0
prefix_2_rd_A	2147483647	1923	0	0
prefix_3_rd_A	2147483647	1940	0	0
prefix_4_rd_A	2147483647	1984	0	0
prefix_5_rd_A	2147483647	2126	0	0
prefix_6_rd_A	2147483647	1978	0	0
prefix_7_rd_A	2147483647	1919	0	0
prefix_8_rd_A	2147483647	2065	0	0
prefix_9_rd_A	2147483647	1881	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1040998	0	0
T22	0	40287	0	0
T38	1454	0	0	0
T55	177893	0	0	0
T57	0	140450	0	0
T62	259437	39134	0	0
T63	0	41785	0	0
T64	0	23511	0	0
T68	0	80975	0	0
T96	480564	0	0	0
T120	0	50903	0	0
T121	0	118196	0	0
T122	0	23406	0	0
T123	0	56144	0	0
T124	113236	0	0	0
T125	124117	0	0	0
T126	536491	0	0	0
T127	779689	0	0	0
T128	50203	0	0	0
T129	134848	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T64	254388	74	0	0
T65	0	133	0	0
T80	0	16	0	0
T82	0	43	0	0
T83	0	20	0	0
T113	0	60	0	0
T114	0	39	0	0
T140	0	60	0	0
T141	0	71	0	0
T142	0	120	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2576	0	0
T64	254388	47	0	0
T65	0	78	0	0
T80	0	6	0	0
T82	0	36	0	0
T83	0	27	0	0
T116	0	22	0	0
T140	0	25	0	0
T141	0	4	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T152	0	1	0	0
T153	0	9	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T64	254388	41	0	0
T65	0	63	0	0
T80	0	5	0	0
T82	0	39	0	0
T83	0	15	0	0
T113	0	33	0	0
T114	0	37	0	0
T140	0	22	0	0
T141	0	7	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1975	0	0
T64	254388	75	0	0
T65	0	91	0	0
T80	0	6	0	0
T82	0	34	0	0
T83	0	24	0	0
T113	0	34	0	0
T114	0	35	0	0
T140	0	57	0	0
T141	0	16	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1929	0	0
T64	254388	52	0	0
T65	0	149	0	0
T80	0	24	0	0
T82	0	38	0	0
T83	0	13	0	0
T113	0	43	0	0
T114	0	44	0	0
T140	0	31	0	0
T141	0	25	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1923	0	0
T64	254388	77	0	0
T65	0	80	0	0
T80	0	22	0	0
T82	0	31	0	0
T83	0	20	0	0
T113	0	41	0	0
T114	0	36	0	0
T140	0	12	0	0
T141	0	29	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T152	0	9	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T64	254388	53	0	0
T65	0	126	0	0
T80	0	13	0	0
T82	0	23	0	0
T83	0	16	0	0
T113	0	49	0	0
T114	0	26	0	0
T140	0	34	0	0
T141	0	14	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1984	0	0
T64	254388	44	0	0
T65	0	113	0	0
T80	0	10	0	0
T82	0	30	0	0
T83	0	16	0	0
T113	0	37	0	0
T114	0	20	0	0
T140	0	32	0	0
T141	0	8	0	0
T142	0	57	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2126	0	0
T64	254388	59	0	0
T65	0	150	0	0
T80	0	9	0	0
T82	0	33	0	0
T83	0	16	0	0
T113	0	47	0	0
T140	0	42	0	0
T141	0	44	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T152	0	3	0	0
T154	0	11	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T64	254388	99	0	0
T65	0	101	0	0
T80	0	12	0	0
T82	0	29	0	0
T83	0	26	0	0
T113	0	41	0	0
T114	0	38	0	0
T140	0	46	0	0
T141	0	21	0	0
T142	0	71	0	0
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T144	660430	0	0	0
T145	143390	0	0	0
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T147	1548	0	0	0
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T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1919	0	0
T64	254388	56	0	0
T65	0	111	0	0
T80	0	3	0	0
T82	0	23	0	0
T83	0	25	0	0
T113	0	45	0	0
T140	0	49	0	0
T141	0	31	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	1	0	0
T155	0	7	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2065	0	0
T64	254388	65	0	0
T65	0	84	0	0
T80	0	13	0	0
T82	0	17	0	0
T83	0	1	0	0
T113	0	38	0	0
T114	0	44	0	0
T140	0	93	0	0
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T145	143390	0	0	0
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T147	1548	0	0	0
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T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	3	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T64	254388	62	0	0
T65	0	87	0	0
T80	0	6	0	0
T82	0	24	0	0
T83	0	19	0	0
T113	0	53	0	0
T114	0	30	0	0
T140	0	38	0	0
T141	0	23	0	0
T143	182866	0	0	0
T144	660430	0	0	0
T145	143390	0	0	0
T146	225245	0	0	0
T147	1548	0	0	0
T148	576390	0	0	0
T149	191041	0	0	0
T150	605870	0	0	0
T151	674093	0	0	0
T154	0	5	0	0