Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265541836

1

T1

27

T2

7957

T3

3683

full_word

186224150

1

T1

167

T2

10990

T3

5963

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	451765706	1			T1	194		T2	18947		T3	9646
auto[TlIntgErrCmd]	79	1			T116	7		T117	9		T118	4
auto[TlIntgErrData]	95	1			T116	5		T117	6		T118	1
auto[TlIntgErrBoth]	106	1			T116	8		T117	5		T118	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232699215

1

T1

79

T2

12529

T3

6588

auto[1]

219066771

1

T1

115

T2

6418

T3

3058

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160777423	1			T1	7		T2	5052		T3	2455
auto[TlIntgErrNone]	partial	auto[1]	104764155	1			T1	20		T2	2905		T3	1228
auto[TlIntgErrNone]	full_word	auto[0]	71921671	1			T1	72		T2	7477		T3	4133
auto[TlIntgErrNone]	full_word	auto[1]	114302457	1			T1	95		T2	3513		T3	1830
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T116	3		T117	6		T118	3
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T116	4		T117	2		T118	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T174	2		T177	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T117	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1			T116	2		T117	4		T174	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T116	2		T117	2		T118	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T174	2		T178	2		T179	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	1		T173	2		T179	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T116	2		T117	2		T118	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T116	5		T117	3		T118	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T179	2		T180	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T118	1		T141	1