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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 321449654 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1242 1242 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 321449654 0 0
T1 3690 98 0 0
T2 175570 10220 0 0
T3 73975 4960 0 0
T4 6240 69 0 0
T7 216334 32169 0 0
T21 325653 327603 0 0
T35 937871 319481 0 0
T36 666695 491054 0 0
T37 154866 141780 0 0
T38 204980 685097 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3690 3542 0 0
T2 175570 175515 0 0
T3 73975 73918 0 0
T4 6240 6167 0 0
T7 216334 216236 0 0
T21 325653 325645 0 0
T35 937871 937799 0 0
T36 666695 666686 0 0
T37 154866 154866 0 0
T38 204980 204974 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3690 3542 0 0
T2 175570 175515 0 0
T3 73975 73918 0 0
T4 6240 6167 0 0
T7 216334 216236 0 0
T21 325653 325645 0 0
T35 937871 937799 0 0
T36 666695 666686 0 0
T37 154866 154866 0 0
T38 204980 204974 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3690 3542 0 0
T2 175570 175515 0 0
T3 73975 73918 0 0
T4 6240 6167 0 0
T7 216334 216236 0 0
T21 325653 325645 0 0
T35 937871 937799 0 0
T36 666695 666686 0 0
T37 154866 154866 0 0
T38 204980 204974 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1242 1242 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T21 1 1 0 0
T35 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 567641685 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 1242 1242 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 567641685 0 0
T1 3690 423 0 0
T2 175570 10220 0 0
T3 73975 4960 0 0
T4 6240 294 0 0
T7 216334 32169 0 0
T21 325653 327603 0 0
T35 937871 319481 0 0
T36 666695 152402 0 0
T37 154866 141780 0 0
T38 204980 685097 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3690 3542 0 0
T2 175570 175515 0 0
T3 73975 73918 0 0
T4 6240 6167 0 0
T7 216334 216236 0 0
T21 325653 325645 0 0
T35 937871 937799 0 0
T36 666695 666686 0 0
T37 154866 154866 0 0
T38 204980 204974 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3690 3542 0 0
T2 175570 175515 0 0
T3 73975 73918 0 0
T4 6240 6167 0 0
T7 216334 216236 0 0
T21 325653 325645 0 0
T35 937871 937799 0 0
T36 666695 666686 0 0
T37 154866 154866 0 0
T38 204980 204974 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3690 3542 0 0
T2 175570 175515 0 0
T3 73975 73918 0 0
T4 6240 6167 0 0
T7 216334 216236 0 0
T21 325653 325645 0 0
T35 937871 937799 0 0
T36 666695 666686 0 0
T37 154866 154866 0 0
T38 204980 204974 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1242 1242 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T21 1 1 0 0
T35 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0

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