Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1001533	0	0
entropy_period_rd_A	2147483647	1314	0	0
intr_enable_rd_A	2147483647	1885	0	0
prefix_0_rd_A	2147483647	1372	0	0
prefix_10_rd_A	2147483647	1270	0	0
prefix_1_rd_A	2147483647	1420	0	0
prefix_2_rd_A	2147483647	1387	0	0
prefix_3_rd_A	2147483647	1403	0	0
prefix_4_rd_A	2147483647	1342	0	0
prefix_5_rd_A	2147483647	1422	0	0
prefix_6_rd_A	2147483647	1303	0	0
prefix_7_rd_A	2147483647	1387	0	0
prefix_8_rd_A	2147483647	1425	0	0
prefix_9_rd_A	2147483647	1323	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1001533	0	0
T27	0	12496	0	0
T28	0	36161	0	0
T54	71503	0	0	0
T57	531629	64172	0	0
T58	0	93925	0	0
T59	0	19633	0	0
T75	253141	0	0	0
T78	1421	0	0	0
T81	0	94595	0	0
T82	0	73278	0	0
T122	0	46739	0	0
T123	0	29614	0	0
T124	0	28633	0	0
T125	893248	0	0	0
T126	125817	0	0	0
T127	430152	0	0	0
T128	103085	0	0	0
T129	605322	0	0	0
T130	994334	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1314	0	0
T82	822287	161	0	0
T83	0	63	0	0
T84	0	72	0	0
T102	0	77	0	0
T117	0	73	0	0
T139	0	15	0	0
T140	0	34	0	0
T141	0	45	0	0
T142	0	30	0	0
T143	0	8	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T82	822287	209	0	0
T83	0	38	0	0
T84	0	58	0	0
T102	0	143	0	0
T117	0	58	0	0
T139	0	9	0	0
T140	0	72	0	0
T141	0	92	0	0
T142	0	38	0	0
T143	0	8	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1372	0	0
T82	822287	181	0	0
T83	0	42	0	0
T84	0	86	0	0
T102	0	74	0	0
T117	0	41	0	0
T139	0	7	0	0
T140	0	39	0	0
T141	0	49	0	0
T142	0	36	0	0
T143	0	5	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1270	0	0
T82	822287	171	0	0
T83	0	29	0	0
T84	0	70	0	0
T102	0	56	0	0
T117	0	67	0	0
T139	0	1	0	0
T140	0	34	0	0
T141	0	32	0	0
T142	0	45	0	0
T143	0	4	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1420	0	0
T82	822287	194	0	0
T83	0	54	0	0
T84	0	80	0	0
T102	0	62	0	0
T117	0	56	0	0
T139	0	4	0	0
T140	0	21	0	0
T141	0	50	0	0
T142	0	63	0	0
T143	0	11	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1387	0	0
T82	822287	208	0	0
T83	0	55	0	0
T84	0	116	0	0
T102	0	63	0	0
T117	0	66	0	0
T140	0	33	0	0
T141	0	46	0	0
T142	0	41	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0
T153	0	3	0	0
T154	0	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1403	0	0
T82	822287	185	0	0
T83	0	61	0	0
T84	0	90	0	0
T102	0	67	0	0
T117	0	29	0	0
T139	0	3	0	0
T140	0	43	0	0
T141	0	43	0	0
T142	0	49	0	0
T143	0	6	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1342	0	0
T82	822287	210	0	0
T83	0	13	0	0
T84	0	86	0	0
T102	0	72	0	0
T117	0	34	0	0
T139	0	8	0	0
T140	0	28	0	0
T141	0	53	0	0
T142	0	21	0	0
T143	0	4	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1422	0	0
T82	822287	194	0	0
T83	0	59	0	0
T84	0	126	0	0
T102	0	47	0	0
T117	0	40	0	0
T139	0	3	0	0
T140	0	46	0	0
T141	0	42	0	0
T142	0	52	0	0
T143	0	7	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T82	822287	160	0	0
T83	0	29	0	0
T84	0	87	0	0
T102	0	46	0	0
T117	0	46	0	0
T139	0	2	0	0
T140	0	35	0	0
T141	0	40	0	0
T142	0	56	0	0
T144	1640	0	0	0
T145	150364	0	0	0
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T147	1701	0	0	0
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T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0
T153	0	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1387	0	0
T82	822287	190	0	0
T83	0	50	0	0
T84	0	58	0	0
T102	0	62	0	0
T117	0	34	0	0
T139	0	3	0	0
T140	0	47	0	0
T141	0	28	0	0
T142	0	50	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
T148	259202	0	0	0
T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0
T153	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1425	0	0
T82	822287	186	0	0
T83	0	32	0	0
T84	0	127	0	0
T102	0	49	0	0
T117	0	42	0	0
T139	0	8	0	0
T140	0	41	0	0
T141	0	37	0	0
T142	0	21	0	0
T144	1640	0	0	0
T145	150364	0	0	0
T146	426115	0	0	0
T147	1701	0	0	0
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T149	420182	0	0	0
T150	337661	0	0	0
T151	346323	0	0	0
T152	175813	0	0	0
T153	0	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1323	0	0
T82	822287	155	0	0
T83	0	26	0	0
T84	0	109	0	0
T102	0	63	0	0
T117	0	33	0	0
T139	0	4	0	0
T140	0	40	0	0
T141	0	31	0	0
T142	0	24	0	0
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T145	150364	0	0	0
T146	426115	0	0	0
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T148	259202	0	0	0
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T150	337661	0	0	0
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T152	175813	0	0	0