Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173362 |
1 |
|
|
T6 |
25 |
|
T8 |
3 |
|
T9 |
10 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
88586 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63629 |
1 |
|
|
T8 |
3 |
|
T9 |
9 |
|
T10 |
78 |
seven_bytes |
2970 |
1 |
|
|
T14 |
34 |
|
T20 |
10 |
|
T110 |
1 |
six_bytes |
3077 |
1 |
|
|
T14 |
34 |
|
T20 |
15 |
|
T110 |
3 |
five_bytes |
2976 |
1 |
|
|
T14 |
26 |
|
T20 |
17 |
|
T110 |
2 |
four_bytes |
3080 |
1 |
|
|
T14 |
31 |
|
T20 |
16 |
|
T110 |
2 |
three_bytes |
3062 |
1 |
|
|
T6 |
1 |
|
T14 |
29 |
|
T20 |
29 |
two_bytes |
2920 |
1 |
|
|
T6 |
1 |
|
T14 |
32 |
|
T20 |
15 |
one_byte |
3062 |
1 |
|
|
T6 |
1 |
|
T14 |
44 |
|
T20 |
19 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169952 |
1 |
|
|
T6 |
23 |
|
T8 |
3 |
|
T9 |
8 |
auto[1] |
3410 |
1 |
|
|
T6 |
2 |
|
T9 |
2 |
|
T10 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173362 |
1 |
|
|
T6 |
25 |
|
T8 |
3 |
|
T9 |
10 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
173355 |
1 |
|
|
T6 |
25 |
|
T8 |
3 |
|
T9 |
10 |
auto[1] |
7 |
1 |
|
|
T175 |
1 |
|
T176 |
2 |
|
T177 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1185 |
1 |
|
|
T9 |
1 |
|
T10 |
2 |
|
T19 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3410 |
1 |
|
|
T6 |
2 |
|
T9 |
2 |
|
T10 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170607 |
1 |
|
|
T6 |
588 |
|
T10 |
74 |
|
T19 |
57 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
85648 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
64761 |
1 |
|
|
T6 |
7 |
|
T10 |
73 |
|
T19 |
55 |
seven_bytes |
2932 |
1 |
|
|
T6 |
15 |
|
T14 |
32 |
|
T20 |
10 |
six_bytes |
2839 |
1 |
|
|
T6 |
14 |
|
T14 |
20 |
|
T20 |
3 |
five_bytes |
2945 |
1 |
|
|
T6 |
17 |
|
T14 |
16 |
|
T20 |
17 |
four_bytes |
2835 |
1 |
|
|
T6 |
18 |
|
T14 |
17 |
|
T20 |
17 |
three_bytes |
2854 |
1 |
|
|
T6 |
16 |
|
T14 |
35 |
|
T20 |
16 |
two_bytes |
2884 |
1 |
|
|
T6 |
6 |
|
T14 |
22 |
|
T20 |
14 |
one_byte |
2909 |
1 |
|
|
T6 |
17 |
|
T14 |
20 |
|
T20 |
15 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167269 |
1 |
|
|
T6 |
580 |
|
T10 |
72 |
|
T19 |
53 |
auto[1] |
3338 |
1 |
|
|
T6 |
8 |
|
T10 |
2 |
|
T19 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170607 |
1 |
|
|
T6 |
588 |
|
T10 |
74 |
|
T19 |
57 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170594 |
1 |
|
|
T6 |
587 |
|
T10 |
74 |
|
T19 |
56 |
auto[1] |
13 |
1 |
|
|
T6 |
1 |
|
T19 |
1 |
|
T178 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1194 |
1 |
|
|
T6 |
1 |
|
T10 |
1 |
|
T19 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3338 |
1 |
|
|
T6 |
8 |
|
T10 |
2 |
|
T19 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342408 |
1 |
|
|
T6 |
1398 |
|
T7 |
1 |
|
T10 |
316 |
auto[1] |
527 |
1 |
|
|
T11 |
50 |
|
T12 |
53 |
|
T13 |
76 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
173123 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
128987 |
1 |
|
|
T6 |
49 |
|
T7 |
1 |
|
T10 |
313 |
seven_bytes |
5824 |
1 |
|
|
T6 |
32 |
|
T14 |
75 |
|
T20 |
17 |
six_bytes |
5923 |
1 |
|
|
T6 |
39 |
|
T14 |
67 |
|
T20 |
12 |
five_bytes |
5918 |
1 |
|
|
T6 |
41 |
|
T14 |
72 |
|
T20 |
11 |
four_bytes |
5733 |
1 |
|
|
T6 |
30 |
|
T14 |
61 |
|
T20 |
13 |
three_bytes |
5880 |
1 |
|
|
T6 |
33 |
|
T14 |
68 |
|
T20 |
10 |
two_bytes |
5688 |
1 |
|
|
T6 |
28 |
|
T14 |
67 |
|
T20 |
11 |
one_byte |
5859 |
1 |
|
|
T6 |
37 |
|
T14 |
66 |
|
T20 |
19 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336185 |
1 |
|
|
T6 |
1380 |
|
T7 |
1 |
|
T10 |
310 |
auto[1] |
6750 |
1 |
|
|
T6 |
18 |
|
T10 |
6 |
|
T19 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342935 |
1 |
|
|
T6 |
1398 |
|
T7 |
1 |
|
T10 |
316 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342910 |
1 |
|
|
T6 |
1398 |
|
T7 |
1 |
|
T10 |
316 |
auto[1] |
25 |
1 |
|
|
T18 |
1 |
|
T175 |
1 |
|
T179 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2398 |
1 |
|
|
T6 |
1 |
|
T10 |
3 |
|
T19 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6750 |
1 |
|
|
T6 |
18 |
|
T10 |
6 |
|
T19 |
12 |