Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257416991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184171605

1

T1

52

T2

195

T3

912108

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228375867	1			T1	14		T2	79		T3	118181
values[0x0]	102377189	1			T1	28		T2	76		T3	551243
values[0x1]	110835540	1			T1	24		T2	59		T3	596330

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199930157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

241658439

1

T1

55

T2

199

T3

122422

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3686244	1			T3	8654		T16	2551		T35	1508
valid_sources[0x01]	1406292	1			T3	8583		T16	2488		T35	1457
valid_sources[0x02]	1451557	1			T3	9264		T4	37		T16	2661
valid_sources[0x03]	1907290	1			T3	8316		T16	2458		T35	1408
valid_sources[0x04]	1804724	1			T3	9304		T4	13		T16	2587
valid_sources[0x05]	1338428	1			T2	1		T3	9329		T4	10
valid_sources[0x06]	1340761	1			T2	1		T3	9455		T16	2441
valid_sources[0x07]	1344441	1			T1	1		T3	8403		T16	2493
valid_sources[0x08]	1380554	1			T2	1		T3	8710		T16	2531
valid_sources[0x09]	1333353	1			T1	3		T3	9089		T16	2484
valid_sources[0x0a]	1342140	1			T3	9707		T4	60		T16	2474
valid_sources[0x0b]	1334867	1			T3	8935		T4	13		T16	2505
valid_sources[0x0c]	1334208	1			T2	2		T3	8833		T16	2609
valid_sources[0x0d]	4155023	1			T3	9103		T4	7		T16	2557
valid_sources[0x0e]	2215116	1			T3	8922		T4	40		T16	2514
valid_sources[0x0f]	1338787	1			T1	2		T3	8579		T4	12
valid_sources[0x10]	1333665	1			T2	1		T3	8491		T16	2519
valid_sources[0x11]	1405357	1			T2	1		T3	9202		T4	33
valid_sources[0x12]	4465774	1			T2	1		T3	8608		T4	25
valid_sources[0x13]	1469979	1			T2	1		T3	9459		T4	10
valid_sources[0x14]	1338572	1			T3	10017		T4	6		T16	2645
valid_sources[0x15]	1331461	1			T2	2		T3	9023		T4	1
valid_sources[0x16]	1337182	1			T3	9105		T4	25		T16	2451
valid_sources[0x17]	1358040	1			T2	2		T3	8790		T4	42
valid_sources[0x18]	1334844	1			T3	8225		T16	2505		T35	1378
valid_sources[0x19]	1344871	1			T2	2		T3	8887		T4	5
valid_sources[0x1a]	1332888	1			T2	7		T3	9316		T16	2488
valid_sources[0x1b]	1335083	1			T2	3		T3	8494		T16	2624
valid_sources[0x1c]	1337954	1			T2	1		T3	9631		T16	2520
valid_sources[0x1d]	1341168	1			T1	5		T3	8625		T16	2705
valid_sources[0x1e]	2221952	1			T2	1		T3	8894		T4	19
valid_sources[0x1f]	1341893	1			T1	2		T3	8714		T16	2474
valid_sources[0x20]	2320836	1			T2	2		T3	9083		T16	2463
valid_sources[0x21]	1572458	1			T3	9309		T16	2634		T35	1345
valid_sources[0x22]	1347698	1			T3	9509		T4	19		T16	2478
valid_sources[0x23]	1372800	1			T2	1		T3	9243		T16	2605
valid_sources[0x24]	1333059	1			T3	8847		T16	2732		T35	1367
valid_sources[0x25]	1341310	1			T2	2		T3	9302		T16	2620
valid_sources[0x26]	1342832	1			T2	1		T3	9151		T16	2647
valid_sources[0x27]	3269421	1			T1	1		T2	1		T3	8489
valid_sources[0x28]	2226176	1			T3	9452		T16	2610		T35	1419
valid_sources[0x29]	1334559	1			T3	9387		T16	2587		T35	1366
valid_sources[0x2a]	1949351	1			T3	9357		T16	2510		T35	1384
valid_sources[0x2b]	4142218	1			T1	2		T2	1		T3	9560
valid_sources[0x2c]	1338928	1			T3	8696		T16	2614		T35	1263
valid_sources[0x2d]	2285913	1			T3	9118		T4	10		T16	2664
valid_sources[0x2e]	3686426	1			T1	2		T2	2		T3	8993
valid_sources[0x2f]	1992340	1			T1	1		T3	9212		T16	2554
valid_sources[0x30]	1341649	1			T3	9541		T4	9		T16	2535
valid_sources[0x31]	1335972	1			T3	8916		T16	2432		T35	1386
valid_sources[0x32]	1338115	1			T3	8640		T16	2617		T35	1491
valid_sources[0x33]	1329310	1			T1	1		T3	9010		T4	5
valid_sources[0x34]	1337566	1			T3	8785		T4	4		T16	2499
valid_sources[0x35]	1339494	1			T3	8427		T16	2578		T35	1388
valid_sources[0x36]	1344162	1			T2	1		T3	8757		T4	13
valid_sources[0x37]	1340636	1			T1	1		T3	8852		T16	2521
valid_sources[0x38]	2238608	1			T1	3		T2	1		T3	9605
valid_sources[0x39]	1386811	1			T3	9464		T16	2518		T35	1364
valid_sources[0x3a]	2174823	1			T1	1		T3	9069		T4	44
valid_sources[0x3b]	1410279	1			T2	2		T3	9178		T16	2528
valid_sources[0x3c]	1333080	1			T3	8735		T16	2658		T35	1501
valid_sources[0x3d]	1333307	1			T3	9134		T4	7		T16	2643
valid_sources[0x3e]	3308394	1			T3	9837		T16	2400		T35	1385
valid_sources[0x3f]	1341217	1			T2	1		T3	8126		T16	2666
valid_sources[0x40]	1336322	1			T2	1		T3	9251		T16	2589
valid_sources[0x41]	1337861	1			T3	8549		T16	2445		T35	1327
valid_sources[0x42]	2230112	1			T2	1		T3	8932		T16	2457
valid_sources[0x43]	1616214	1			T3	9304		T4	64		T16	2555
valid_sources[0x44]	5259369	1			T3	8531		T4	1		T16	2730
valid_sources[0x45]	1341985	1			T3	8258		T16	2575		T35	1409
valid_sources[0x46]	1785543	1			T3	8812		T4	41		T16	2727
valid_sources[0x47]	1369361	1			T3	9455		T4	35		T16	2477
valid_sources[0x48]	1329826	1			T2	2		T3	9042		T16	2487
valid_sources[0x49]	1338241	1			T2	1		T3	8936		T16	2516
valid_sources[0x4a]	3970688	1			T3	9355		T4	17		T16	2469
valid_sources[0x4b]	1334870	1			T2	2		T3	9177		T4	10
valid_sources[0x4c]	1435327	1			T3	8634		T16	2605		T35	1468
valid_sources[0x4d]	1341755	1			T3	9219		T16	2520		T35	1493
valid_sources[0x4e]	2198986	1			T2	8		T3	8937		T16	2617
valid_sources[0x4f]	1450329	1			T1	2		T3	9702		T16	2458
valid_sources[0x50]	3744801	1			T1	1		T3	9086		T4	27
valid_sources[0x51]	1421513	1			T2	2		T3	9073		T16	2551
valid_sources[0x52]	1336671	1			T2	2		T3	9493		T16	2523
valid_sources[0x53]	1334634	1			T3	8943		T4	33		T16	2476
valid_sources[0x54]	2178159	1			T2	4		T3	9381		T16	2642
valid_sources[0x55]	1336381	1			T1	1		T2	1		T3	9177
valid_sources[0x56]	1348405	1			T3	8759		T4	8		T16	2619
valid_sources[0x57]	3295176	1			T3	9039		T16	2518		T35	1330
valid_sources[0x58]	1335934	1			T2	2		T3	9170		T16	2583
valid_sources[0x59]	1343511	1			T3	9632		T4	70		T16	2544
valid_sources[0x5a]	3668250	1			T3	8747		T16	2613		T35	1391
valid_sources[0x5b]	1339675	1			T3	9199		T16	2658		T35	1368
valid_sources[0x5c]	1382469	1			T2	4		T3	9652		T16	2486
valid_sources[0x5d]	2323739	1			T3	8993		T16	2561		T35	1404
valid_sources[0x5e]	1439488	1			T2	2		T3	9819		T16	2483
valid_sources[0x5f]	1342177	1			T2	1		T3	9161		T16	2574
valid_sources[0x60]	1346968	1			T2	8		T3	9188		T16	2496
valid_sources[0x61]	1341378	1			T1	1		T2	1		T3	8734
valid_sources[0x62]	1334268	1			T2	1		T3	9195		T4	19
valid_sources[0x63]	1379921	1			T3	9859		T16	2639		T35	1396
valid_sources[0x64]	1425211	1			T1	2		T2	2		T3	8971
valid_sources[0x65]	1784754	1			T3	9376		T16	2482		T35	1391
valid_sources[0x66]	1334429	1			T2	2		T3	8811		T4	15
valid_sources[0x67]	1333361	1			T3	8335		T4	19		T16	2601
valid_sources[0x68]	1336615	1			T3	9473		T16	2553		T35	1379
valid_sources[0x69]	1480271	1			T3	8888		T16	2524		T35	1310
valid_sources[0x6a]	1343209	1			T3	9906		T4	23		T16	2600
valid_sources[0x6b]	1930164	1			T1	1		T2	1		T3	9379
valid_sources[0x6c]	1339658	1			T3	8609		T16	2601		T35	1353
valid_sources[0x6d]	1329802	1			T2	2		T3	8767		T4	18
valid_sources[0x6e]	1342670	1			T3	9579		T16	2636		T35	1363
valid_sources[0x6f]	1355192	1			T1	1		T3	9658		T4	17
valid_sources[0x70]	1476035	1			T2	2		T3	9506		T16	2686
valid_sources[0x71]	1335054	1			T3	8614		T16	2626		T35	1461
valid_sources[0x72]	1344590	1			T3	9428		T4	3		T16	2577
valid_sources[0x73]	1333338	1			T2	3		T3	8948		T16	2681
valid_sources[0x74]	2226214	1			T3	8979		T4	27		T16	2563
valid_sources[0x75]	1341676	1			T3	9185		T16	2472		T35	1342
valid_sources[0x76]	2226328	1			T2	1		T3	9353		T16	2607
valid_sources[0x77]	1546416	1			T2	1		T3	9384		T4	108
valid_sources[0x78]	1336926	1			T2	1		T3	9640		T16	2443
valid_sources[0x79]	1957147	1			T1	2		T2	1		T3	9163
valid_sources[0x7a]	3355999	1			T2	2		T3	9447		T16	2503
valid_sources[0x7b]	1505294	1			T1	2		T3	9138		T16	2517
valid_sources[0x7c]	1339015	1			T3	9374		T4	4		T16	2610
valid_sources[0x7d]	1340611	1			T3	9215		T16	2614		T35	1430
valid_sources[0x7e]	1337135	1			T3	9087		T4	15		T16	2569
valid_sources[0x7f]	1334777	1			T3	9255		T4	4		T16	2631
valid_sources[0x80]	1457056	1			T2	2		T3	9128		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70940617

1

T1

4

T2

73

T3

336895

values[0x0]

all_enables

biggest_size

60788154

1

T1

25

T2

71

T3

312247

values[0x1]

all_enables

biggest_size

52442834

1

T1

23

T2

51

T3

262966