Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262118332

1

T1

14

T2

19

T3

141728

full_word

184466781

1

T1

52

T2

195

T3

912108

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	446584833	1			T1	66		T2	214		T3	232938
auto[TlIntgErrCmd]	96	1			T129	2		T130	5		T131	4
auto[TlIntgErrData]	95	1			T129	1		T130	2		T131	3
auto[TlIntgErrBoth]	89	1			T129	7		T130	3		T131	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229292437

1

T1

14

T2

79

T3

118181

auto[1]

217292676

1

T1

52

T2

135

T3

114757

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158277503	1			T1	10		T2	6		T3	844920
auto[TlIntgErrNone]	partial	auto[1]	103840578	1			T1	4		T2	13		T3	572360
auto[TlIntgErrNone]	full_word	auto[0]	71014801	1			T1	4		T2	73		T3	336895
auto[TlIntgErrNone]	full_word	auto[1]	113451951	1			T1	48		T2	122		T3	575213
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T129	2		T130	4		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T130	1		T131	2		T182	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T182	1		T183	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T182	1		T187	1		T190	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T129	1		T130	1		T131	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T130	1		T182	3		T167	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T184	1		T191	1		T192	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T131	1		T183	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T129	2		T130	3		T183	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T129	4		T131	2		T182	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T192	1		T190	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T129	1		T131	1		T182	1