Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1090973	0	0
entropy_period_rd_A	2147483647	1301	0	0
intr_enable_rd_A	2147483647	1875	0	0
prefix_0_rd_A	2147483647	994	0	0
prefix_10_rd_A	2147483647	1274	0	0
prefix_1_rd_A	2147483647	967	0	0
prefix_2_rd_A	2147483647	1060	0	0
prefix_3_rd_A	2147483647	1147	0	0
prefix_4_rd_A	2147483647	1138	0	0
prefix_5_rd_A	2147483647	1154	0	0
prefix_6_rd_A	2147483647	1186	0	0
prefix_7_rd_A	2147483647	1177	0	0
prefix_8_rd_A	2147483647	1134	0	0
prefix_9_rd_A	2147483647	1057	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1090973	0	0
T6	742364	109413	0	0
T7	3733	0	0	0
T8	2829	0	0	0
T10	0	77647	0	0
T37	801922	0	0	0
T38	933859	0	0	0
T40	0	61037	0	0
T44	331101	0	0	0
T45	17433	0	0	0
T50	178460	0	0	0
T51	464097	0	0	0
T111	615089	0	0	0
T135	0	70608	0	0
T136	0	64792	0	0
T137	0	27965	0	0
T138	0	76721	0	0
T139	0	27740	0	0
T140	0	63762	0	0
T141	0	45122	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1301	0	0
T95	6636	16	0	0
T97	2187	2	0	0
T130	11600	43	0	0
T131	12262	48	0	0
T159	1828	13	0	0
T160	8079	26	0	0
T161	12181	28	0	0
T162	7344	29	0	0
T163	7040	12	0	0
T164	1977	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1875	0	0
T95	6636	11	0	0
T97	2187	2	0	0
T130	11600	68	0	0
T132	778	9	0	0
T159	1828	18	0	0
T160	8079	17	0	0
T161	12181	105	0	0
T162	7344	38	0	0
T165	13645	7	0	0
T166	1111	12	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	994	0	0
T95	6636	10	0	0
T97	2187	5	0	0
T130	11600	39	0	0
T131	12262	34	0	0
T159	1828	1	0	0
T160	8079	12	0	0
T161	12181	36	0	0
T162	7344	14	0	0
T163	7040	6	0	0
T164	1977	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1274	0	0
T95	6636	18	0	0
T97	2187	5	0	0
T130	11600	46	0	0
T131	12262	38	0	0
T159	1828	4	0	0
T160	8079	8	0	0
T161	12181	59	0	0
T162	7344	26	0	0
T163	7040	10	0	0
T164	1977	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	967	0	0
T95	6636	12	0	0
T97	2187	6	0	0
T130	11600	39	0	0
T131	12262	55	0	0
T159	1828	2	0	0
T160	8079	11	0	0
T161	12181	42	0	0
T162	7344	14	0	0
T163	7040	2	0	0
T164	1977	1	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1060	0	0
T95	6636	18	0	0
T97	2187	3	0	0
T130	11600	27	0	0
T131	12262	30	0	0
T159	1828	6	0	0
T160	8079	12	0	0
T161	12181	60	0	0
T162	7344	18	0	0
T163	7040	6	0	0
T164	1977	2	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1147	0	0
T95	6636	17	0	0
T97	2187	4	0	0
T130	11600	55	0	0
T131	12262	37	0	0
T159	1828	3	0	0
T160	8079	15	0	0
T161	12181	68	0	0
T162	7344	8	0	0
T163	7040	15	0	0
T164	1977	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138	0	0
T95	6636	24	0	0
T97	2187	3	0	0
T130	11600	43	0	0
T131	12262	53	0	0
T159	1828	2	0	0
T160	8079	22	0	0
T161	12181	55	0	0
T162	7344	15	0	0
T163	7040	17	0	0
T164	1977	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1154	0	0
T95	6636	6	0	0
T97	2187	6	0	0
T130	11600	50	0	0
T131	12262	22	0	0
T159	1828	3	0	0
T160	8079	25	0	0
T161	12181	83	0	0
T162	7344	17	0	0
T163	7040	3	0	0
T164	1977	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1186	0	0
T95	6636	33	0	0
T97	2187	2	0	0
T130	11600	37	0	0
T131	12262	50	0	0
T159	1828	4	0	0
T160	8079	17	0	0
T161	12181	67	0	0
T162	7344	12	0	0
T163	7040	22	0	0
T164	1977	5	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1177	0	0
T95	6636	14	0	0
T130	11600	31	0	0
T131	12262	42	0	0
T160	8079	15	0	0
T161	12181	76	0	0
T162	7344	18	0	0
T163	7040	4	0	0
T164	1977	1	0	0
T167	11617	33	0	0
T168	2854	5	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1134	0	0
T95	6636	17	0	0
T97	2187	2	0	0
T130	11600	34	0	0
T131	12262	36	0	0
T159	1828	5	0	0
T160	8079	16	0	0
T161	12181	64	0	0
T162	7344	26	0	0
T163	7040	3	0	0
T165	13645	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1057	0	0
T95	6636	9	0	0
T130	11600	58	0	0
T131	12262	28	0	0
T159	1828	5	0	0
T160	8079	10	0	0
T161	12181	22	0	0
T162	7344	20	0	0
T163	7040	4	0	0
T165	13645	6	0	0
T169	12112	5	0	0